Datasheet

6 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
Tables
1-1 Intel
®
Xeon
®
Processor 3400 Series Supported Memory Summary .................................12
1-2 Related Documents...................................................................................................18
2-1 Supported DIMM Module Configurations.......................................................................19
2-2 DDR3 System Memory Timing Support .......................................................................20
2-3 System Memory Pre-Charge Power Down Support.........................................................23
2-4 Processor Reference Clock Requirements.....................................................................28
4-1 Processor Core/Package State Support........................................................................33
4-2 G, S, and C State Combinations..................................................................................34
4-3 Coordination of Thread Power States at the Core Level..................................................36
4-4 P_LVLx to MWAIT Conversion.....................................................................................37
4-5 Coordination of Core Power States at the Package Level ................................................39
4-6 Targeted Memory State Conditions .............................................................................42
6-1 Signal Description Buffer Types..................................................................................47
6-2 Memory Channel A ...................................................................................................48
6-3 Memory Channel B ...................................................................................................49
6-4 Memory Reference and Compensation.........................................................................50
6-5 Reset and Miscellaneous Signals.................................................................................50
6-6 PCI Express* Based Interface Signals..........................................................................51
6-7 DMI — Processor to PCH Serial Interface .....................................................................52
6-8 PLL Signals..............................................................................................................52
6-9 Intel
®
Flexible Display Interface.................................................................................52
6-10JTAG/ITP.................................................................................................................53
6-11Error and Thermal Protection .....................................................................................54
6-12Power Sequencing....................................................................................................55
6-13Processor Core Power Signals.....................................................................................55
6-14Graphics and Memory Power Signals...........................................................................57
6-15Ground and NCTF.....................................................................................................58
6-16Processor Internal Pull Up/Pull Down...........................................................................58
7-1 VRD 11.1/11.0 Voltage Identification Definition ............................................................61
7-2 Market Segment Selection Truth Table for MSID[2:0]....................................................63
7-3 Signal Groups 1 .......................................................................................................65
7-4 Processor Absolute Minimum and Maximum Ratings......................................................67
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications ....................68
7-6 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications ......................69
7-7 VCC Static and Transient Tolerance.............................................................................70
7-8 DDR3 Signal Group DC Specifications..........................................................................72
7-9 Control Sideband and TAP Signal Group DC Specifications..............................................73
7-10PCI Express DC Specifications....................................................................................74
7-11PECI DC Electrical Limits ...........................................................................................75
8-1 Signals Not Used by the Intel
®
Xeon
®
Processor 3400 Series.........................................77
8-2 Processor Pin List by Pin Name...................................................................................82