Datasheet

Electrical Specifications
70 Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
Notes:
1. The V
CC_MIN
and V
CC_MAX
loadlines represent static and transient limits.
2. This table is intended to aid in reading discrete points on Figure 7-1.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for socket load line
guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR
implementation.
Table 7-7. V
CC
Static and Transient Tolerance
I
CC
(A)
Voltage Deviation from VID Setting
1, 2, 3
V
CC_Max
(V)
1.40 mΩ
V
CC_Typ
(V)
1.40 mΩ
V
CC_Min
(V)
1.40 mΩ
0 0.000 -0.019 -0.038
5 -0.007 -0.026 -0.045
10 -0.014 -0.033 -0.052
15 -0.021 -0.040 -0.059
20 -0.028 -0.047 -0.066
25 -0.035 -0.054 -0.073
30 -0.042 -0.061 -0.080
35 -0.049 -0.068 -0.087
40 -0.056 -0.075 -0.094
45 -0.063 -0.082 -0.101
50 -0.070 -0.089 -0.108
55 -0.077 -0.096 -0.115
60 -0.084 -0.103 -0.122
65 -0.091 -0.110 -0.129
70 -0.098 -0.117 -0.136
75 -0.105 -0.124 -0.143
80 -0.112 -0.131 -0.150
85 -0.119 -0.138 -0.157
90 -0.126 -0.145 -0.164
95 -0.133 -0.152 -0.171
100 -0.140 -0.159 -0.178
110 -0.147 -0.166 -0.185