2nd Generation Intel® Core™ Processor Family Desktop Datasheet, Volume 1 Supporting Intel® Core™ i7, i5 and i3 Desktop Processor Series This is Volume 1 of 2 January 2011 Document Number: 324641-001
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Contents 1 Introduction .............................................................................................................. 9 1.1 Processor Feature Details ................................................................................... 11 1.1.1 Supported Technologies .......................................................................... 11 1.2 Interfaces ........................................................................................................ 11 1.2.
2.5 2.6 2.4.1.2 3D Pipeline ...............................................................................29 2.4.1.3 Video Engine ............................................................................30 2.4.1.4 2D Engine ................................................................................30 2.4.2 Processor Graphics Display ......................................................................31 2.4.2.1 Display Planes .......................................................................
4.4 4.5 4.6 4.7 4.3.2.1 Initialization Role of CKE ............................................................ 54 4.3.2.2 Conditional Self-Refresh ............................................................ 54 4.3.2.3 Dynamic Power-down Operation ................................................. 54 4.3.2.4 DRAM I/O Power Management .................................................... 54 PCIe* Power Management ..................................................................................
Figures 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 4-1 4-2 4-3 7-1 7-2 8-1 8-2 8-3 8-4 6 2nd Generation Intel® Core™ Processor Family Desktop Platform ..................................10 Intel® Flex Memory Technology Operation ..................................................................21 PCI Express* Layering Diagram.................................................................................24 Packet Flow through the Layers.................................................................................
Tables 1-1 1-2 2-1 2-2 2-3 2-4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 8-1 9-1 9-2 PCIe Supported Configurations in Desktop Products..................................................... 12 Related Documents ................................................................................................. 18 Supported UDIMM Module Configurations ...............................................
Revision History Revision Number 001 Description Revision Date January 2011 Initial release §§ 8 Datasheet, Volume 1
Introduction 1 Introduction The 2nd Generation Intel® Core™ processor family desktop is the next generation of 64-bit, multi-core desktop processor built on 32- nanometer process technology. Based on a new micro-architecture, the processor is designed for a two-chip platform consisting of a processor and Platform Controller Hub (PCH). The platform enables higher performance, lower cost, easier validation, and improved x-y footprint.
Introduction Figure 1-1. 2nd Generation Intel® Core™ Processor Family Desktop Platform PCI Express* 2.0 1 x16 or 2x8 DDR3 Discrete Graphics (PEG) Processor PECI Intel® Flexible Display Interface DMI2 x4 Serial ATA Intel® Management Engine Digital Display x 3 USB 2.0 Platform Controller Hub (PCH) LVDS Flat Panel Intel®HD Audio Analog CRT PCI SPI Flash x 2 SMBUS 2.0 SPI Controller Link 1 FWH PCI Express* WiFi / WiMax LPC 8 PCI Express* 2.
Introduction 1.1 Processor Feature Details • Four or two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.1 Supported Technologies • Intel® Virtualization Technology for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT-x) • Intel® Active Management Technology 7.0 (Intel® AMT 7.
Introduction • Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices) • Command launch modes of 1n/2n • On-Die Termination (ODT) • Asynchronous ODT • Intel® Fast Memory Access (Intel® FMA) — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling 1.2.2 PCI Express* • The PCI Express* port(s) are fully-compliant to the PCI Express Base Specification, Revision 2.0. • Processor with desktop PCH supported configurations Table 1-1.
Introduction • Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering) • Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0 — DMI -> PCI Express* Port 0 • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are non
Introduction • Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port DMA, floppy drive, and LPC bus masters • DC coupling – no capacitors between the processor and the PCH • Polarity inversion • PCH end-to-end lane reversal across the link • Supports Half Swing “low-power/low-voltage” 1.2.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master.
Introduction 1.3 Power Management Support 1.3.1 Processor Core • Full support of ACPI C-states as implemented by the following processor C-states — C0, C1, C1E, C3, C6 • Enhanced Intel SpeedStep® Technology 1.3.2 System • S0, S3, S4, S5 1.3.3 Memory Controller • Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) • Dynamic power-down 1.3.4 PCI Express* • L0s and L1 ASPM power management capability 1.3.5 DMI • L0s and L1 ASPM power management capability 1.3.
Introduction 1.5 Package • The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155). See the 2nd Generation Intel® Core™ Processor and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines for complete details on package. 1.
Introduction Term Description PEG PCI Express* Graphics. External Graphics using PCI Express* Architecture. A high-speed serial interface whose configuration is software compatible with the existing PCI specifications. Processor The 64-bit, single-core or multi-core component (package). Processor Core The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache.
Introduction 1.7 Related Documents Refer to Table 1-2 for additional information. Table 1-2. Related Documents Document Document Number/ Location 2nd Generation Intel® Core™ Processor Family Desktop Datasheet, Volume 2 http://download.intel.com/design /processor/datashts/324642.pdf 2nd Generation Intel® Core™ Processor Family Desktop Specification Update http://download.intel.com/design /processor/specupdt/324643.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependant on the PCH SKU in the target platform. Refer to Chapter 1 for supported memory configuration details.
Interfaces Table 2-2.
Interfaces 2.1.3 System Memory Organization Modes The IMC supports two memory organization modes—single-channel and dual-channel. Depending upon how the DIMM Modules are populated in each memory channel, a number of different configurations can exist. 2.1.3.1 Single-Channel Mode In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order, but not both. 2.1.3.
Interfaces 2.1.3.2.1 Dual-Channel Symmetric Mode Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned.
Interfaces 2.1.5.2 Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate, Precharge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command. Multiple commands can be issued in an overlapping manner, increasing the efficiency of system memory protocol. 2.1.5.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1 for details. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged.
Interfaces packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-3. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4.
Interfaces 2.2.4 PCI Express Lanes Connection Figure 2-5 demonstrates the PCIe lanes mapping. Figure 2-5. PCIe Typical Operation 16 lanes Mapping 0 1 2 3 4 5 0 2.
Interfaces 2.3.3 DMI Link Down The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH. Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal.
Interfaces 2.4.1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the following performance and power-management enhancements: • Up to 12 Execution units (EUs) • Hierarchal-Z • Video quality enhancements 2.4.1.1 3D Engine Execution Units • Supports up to 12 EUs.
Interfaces 2.4.1.2.6 Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible.
Interfaces 2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes • DisplayPort and Intel® FDI Figure 2-7. Processor Display Block Diagram 2.4.2.
Interfaces 2.4.2.1.4 VGA VGA is used for boot, safe mode, legacy games, etc. It can be changed by an application without OS/driver notification, due to legacy requirements. 2.4.2.2 Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed. This is clocked by the Display Reference clock inputs.
Interfaces 2.5 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (processor) and a PECI master. The processor implements a PECI interface to: • Allow communication of processor thermal and other information to the PECI master. • Read averaged Digital Thermal Sensor (DTS) values for fan speed control. 2.6 Interface Clocking 2.6.1 Internal Clocking Requirements Table 2-4.
Interfaces 34 Datasheet, Volume 1
Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
Technologies 3.1.
Technologies 3.1.4 Intel® VT-d Features The processor supports the following Intel VT-d features: • Memory controller and Processor Graphics comply with Intel® VT-d 1.2 specification. • Two VT-d DMA remap engines.
Technologies 3.2 Intel® Trusted Execution Technology (Intel® TXT) Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements that provide the building blocks for creating trusted platforms. The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision.
Technologies 3.4 Intel® Turbo Boost Technology Intel® Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency/render clock if it is operating below power, temperature, and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. Maximum frequency is dependant on the SKU and number of active cores.
Technologies 3.5 Intel® Advanced Vector Extensions (AVX) Intel® Advanced Vector Extensions (AVX) is the latest expansion of the Intel instruction set. It extends the Intel® Streaming SIMD Extensions (SSE) from 128-bit vectors into 256-bit vectors. Intel AVX addresses the continued need for vector floating-point performance in mainstream scientific and engineering numerical applications, visual processing, recognition, data-mining/synthesis, gaming, physics, cryptography and other areas of applications.
Technologies 3.7 Intel® 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides a key mechanism for interrupt delivery. This extension is intended primarily to increase processor addressability.
Technologies The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new Operating System and a new BIOS are both needed, with special support for the x2APIC mode. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations. Note: Intel x2APIC technology may not be available on all processor SKUs.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State G0/S0 G1/S3-Cold Description Full On Suspend-to-RAM (STR).
Power Management 4.1.3 Integrated Memory Controller States Table 4-3. Integrated Memory Controller States State Power up Pre-charge Power-down Active PowerDown Self-Refresh Description CKE asserted. Active mode. CKE de-asserted (not self-refresh) with all banks closed. CKE de-asserted (not self-refresh) with minimum one bank active. CKE de-asserted using device self-refresh. 4.1.4 PCIe Link States Table 4-4. PCIe Link States State Description L0 Full on – Active transfer state.
Power Management 4.1.7 Interface State Combinations Table 4-7. G, S and C State Combinations 4.
Power Management 4.2.2 Low-Power Idle States When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread-level C-states are available if Intel Hyper-Threading Technology is enabled.
Power Management Table 4-8. Coordination of Thread Power States at the Core Level Processor Core C-State Thread 1 C0 C1 C3 C6 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C3 C0 C11 C3 C3 C6 C0 C11 C3 C6 Thread 0 Note: 1. If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher. 4.2.
Power Management 4.2.4 Core C-states The following are general rules for all core C-states, unless specified otherwise: • A core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-7.
Power Management There are two C-State auto-demotion options: • C6 to C3 • C6/C3 To C1 The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s immediate residency history. Upon each core C6 request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established. At that point, a core is allowed to go into C3/C6. Each option can be run concurrently or individually. This feature is disabled by default.
Power Management Table 4-10. Coordination of Core Power States at the Package Level Core 1 Package C-State C0 C1 C3 C6 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C3 C0 C11 C3 C3 C0 1 C3 C6 Core 0 C6 C1 Note: 1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher. Figure 4-3. Package C-State Entry and Exit C0 C3 C1 4.2.5.1 C6 Package C0 This is the normal operating state for the processor.
Power Management 4.2.5.2 Package C1/C1E No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: • At least one core is in the C1 state. • The other cores are in a C1 or lower power state.
Power Management 4.3 IMC Power Management The main memory is power managed during normal operation and in low-power ACPI Cx states. 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as DIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are: • Reduced power consumption.
Power Management The processor supports 5 different types of power-down. The different modes are the power-down modes supported by DDR3 and combinations of these. The type of CKE power-down is defined by the configuration. The are options are: 1. No power-down 2. APD: The rank enters power-down as soon as idle-timer expires, no matter what is the bank status 3. PPD: When idle timer expires the MC sends PRE-all to rank and then enters powerdown 4.
Power Management 4.3.2.1 Initialization Role of CKE During power-up, CKE is the only input to the SDRAM that has its level recognized (other than the DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during powerup. CKE signals remain LOW (while any reset is active) until the BIOS writes to a configuration register.
Power Management 4.5 DMI Power Management • Active power management support using L0s/L1 state. 4.6 Graphics Power Management 4.6.1 Intel® Rapid Memory Power Management (RMPM) (also know as CxSR) The Intel® Rapid Memory Power Management puts rows of memory into self refresh mode during C3/C6 to allow the system to remain in the lower power states longer. Desktop processors routinely save power during runtime conditions by entering the C3, C6 state.
Power Management 4.6.5 Intel® Graphics Dynamic Frequency Intel® Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and/or voltage above the ensured processor and graphics frequency for the given part. Intel® Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance.
Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the 2nd Generation Intel® Core™ Processor Family Desktop and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines.
Thermal Management 58 Datasheet, Volume 1
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal (see Table 6-1). Table 6-1.
Signal Description 6.1 System Memory Interface Table 6-2. Memory Channel A Signal Name Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SA_WE# Write Enable Control Signal: This signal is used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands. O DDR3 SA_RAS# RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.
Signal Description Table 6-3. Memory Channel B Signal Name Description Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_WE# Write Enable Control Signal: This signal is used with SB_RAS# and SB_CAS# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_RAS# RAS Control Signal: This signal is used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.
Signal Description 6.3 Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals Signal Name Direction/ Buffer Type Description Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for this lane. • CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
Signal Description 6.4 PCI Express* Based Interface Signals Table 6-6.
Signal Description 6.6 DMI Table 6-8. DMI - Processor to PCH Serial Interface Signal Name DMI_RX[3:0] DMI_RX#[3:0] DMI Input from PCH: Direct Media Interface receive differential pair. I DMI DMI_TX[3:0] DMI_TX#[3:0] DMI Output to PCH: Direct Media Interface transmit differential pair. O DMI 6.7 PLL Signals Table 6-9. PLL Signals Signal Name BCLK BCLK# 6.
Signal Description 6.9 Error and Thermal Protection Table 6-11. Error and Thermal Protection 6.10 Signal Name Description Direction/ Buffer Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.
Signal Description 6.11 Processor Power Signals Table 6-13. Processor Power Signals Signal Name VCC 6.12 Direction/ Buffer Type Description Processor core power rail Ref VCCIO Processor power for I/O Ref VDDQ Processor I/O supply voltage for DDR3 Ref VAXG Graphics core power supply.
Signal Description 6.14 Processor Internal Pull Up/Pull Down Table 6-16.
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Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Lands The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3 Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core operating frequency, memory controller frequency, system agent frequencies, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency.
Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3) VID VID VID VID 7 6 5 4 VID VID VID 3 2 1 VID 0 HEX VCC_MAX VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 0 0 0 0 0 0 0 0 0 0.00000 1 0 0 0 0 0 0 0 8 0 0.88500 0 0 0 0 0 0 0 1 0 1 0.25000 1 0 0 0 0 0 0 1 8 1 0.89000 0 0 0 0 0 0 1 0 0 2 0.25500 1 0 0 0 0 0 1 0 8 2 0.89500 0 0 0 0 0 0 1 1 0 3 0.
Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 2 of 3) VID VID VID VID 7 6 5 4 VID VID VID 3 2 1 VID 0 HEX VCC_MAX 0.45500 VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 VCC_MAX A 1.09500 0 0 1 0 1 0 1 0 2 A 0 0 1 0 1 0 1 1 2 B 0.46000 1 0 1 0 1 0 1 1 A B 1.10000 0 0 1 0 1 1 0 0 2 C 0.46500 1 0 1 0 1 1 0 0 A C 1.10500 0 0 1 0 1 1 0 1 2 D 0.
Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 3 of 3) VID VID VID VID 7 6 5 4 VID VID VID 3 2 1 VID 0 HEX VCC_MAX VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 1 0 1 0 1 0 1 5 5 0.67000 1 1 0 1 0 1 0 1 D 5 1.31000 0 1 0 1 0 1 1 0 5 6 0.67500 1 1 0 1 0 1 1 0 D 6 1.31500 0 1 0 1 0 1 1 1 5 7 0.68000 1 1 0 1 0 1 1 1 D 7 1.32000 0 1 0 1 1 0 0 0 5 8 0.
Electrical Specifications 7.5 System Agent (SA) VCC VID The VCCSA is configured by the processor output pin VCCSA_VID. VCCSA_VID output default logic state is low for the processors; logic high is reserved for future compatibility. Table 7-2 specifies the different VCCSA_VID configurations. Table 7-2. VCCSA_VID configuration Processor Family 2nd Generation Intel family desktop ® Core™ processor Future Intel processors VCCSA_VID Selected VCCSA 0 0.925 V 1 Note 1 Notes: 1.
Electrical Specifications 7.7 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. Table 7-3.
Electrical Specifications Table 7-3.
Electrical Specifications 7.9 Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity that the device is exposed to while being stored in a moisture barrier bag. The specified storage conditions are for component level prior to board attach. Table 7-4 specifies absolute maximum and minimum storage temperature limits that represent the maximum or minimum device condition beyond which damage, latent or otherwise, may occur.
Electrical Specifications 7.10 DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-5, Table 7-6, and Table 7-7. The DC specifications for the DDR3 signals are listed in Table 7-8 Control Sideband and Test Access Port (TAP) are listed in Table 7-9.
Electrical Specifications Table 7-5.
Electrical Specifications Table 7-6. Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note 1 2 VCCSA Voltage for the system agent 0.879 0.925 0.971 V VDDQ Processor I/O supply voltage for DDR3 1.425 1.5 1.575 V 1.71 1.8 1.89 V -2/-3% 1.05 +2/+3% V Current for the system agent — — 8.8 A ISA_TDC Sustained current for the system agent — — 8.2 A IDDQ Processor I/O supply current for DDR3 — — 4.
Electrical Specifications Table 7-7. Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications Symbol VAXG GFX_VID Range LLAXG VAXGTOB VAXGRipple Parameter GFX_VID Range for VCCAXG Min Typ Max Unit Note2 0.2500 — 1.5200 V 1 4.1 m 3, 4 19 11.
Electrical Specifications Table 7-8. DDR3 Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Units Notes1,9 RON_UP(CMD) DDR3 command buffer pull-up resistance 16 20 23 Ω 5 RON_DN(CMD) DDR3 command buffer pulldown resistance 16 20 24 Ω 5 RON_UP(CTL) DDR3 control buffer pull-up resistance 16 20 23 Ω 5 RON_DN(CTL) DDR3 control buffer pull-down resistance 16 20 24 Ω 5 Input Low Voltage for SM_DRAMPWROK — — VDDQ *.55 – 0.
Electrical Specifications Table 7-10. PCIe DC Specifications Min Typ Max Units Notes1,11 Low differential peak to peak Tx voltage swing 0.4 0.5 0.6 V 3 VTX-DIFF-p-p Differential peak to peak Tx voltage swing 0.8 1 1.
Electrical Specifications 7.11 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications 7.11.2 DC Characteristics The PECI interface operates at a nominal voltage set by VCCIO. The set of DC electrical specifications shown in Table 7-11 is used with devices normally operating from a VCCIO interface supply. VCCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the processor installed in the system. For specific nominal VCCIO levels, refer to Table 7-6. Table 7-11.
Electrical Specifications 86 Datasheet, Volume 1
Processor Pin and Signal Information 8 Processor Pin and Signal Information 8.1 Processor Pin Assignments The processor pinmap quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-1 provides a listing of all processor pins ordered alphabetically by pin name. Note: Pin names SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are RSVD on desktop processors.
Processor Pin and Signal Information Figure 8-1.
Processor Pin and Signal Information Figure 8-2.
Processor Pin and Signal Information Figure 8-3.
Processor Pin and Signal Information Figure 8-4.
Processor Pin and Signal Information Table 8-1. Pin Name 92 Processor Pin List by Pin Name Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Pin # Buffer Type Dir. Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Pin # Buffer Type Dir. SA_DQ[26] AV9 DDR3 I/O SA_DQS[6] Pin Name SA_DQ[27] AU9 DDR3 I/O SA_DQ[28] AV7 DDR3 I/O SA_DQ[29] AW7 DDR3 I/O SA_DQ[30] AW9 DDR3 Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Name Pin Name Table 8-1. Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name 98 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name VCC Processor Pin List by Pin Name Dir. Table 8-1.
Processor Pin and Signal Information Table 8-1. Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1.
Processor Pin and Signal Information Table 8-1. Pin Name 102 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name 104 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type VSS V5 GND VSS W6 GND VSS Y5 GND VSS Y8 GND VSS_NCTF A4 GND VSS_NCTF AV39 GND VSS_NCTF AY37 GND VSS_NCTF Dir.
Processor Pin and Signal Information 106 Datasheet, Volume 1
DDR Data Swizzling 9 DDR Data Swizzling To achieve better memory performance and better memory timing, Intel design performed the DDR Data pin swizzeling that will allow a better use of the product across different platforms. Swizzeling has no effect on functional operation and is invisible to the OS/SW. However, during debug, swizzeling needs to be taken into consideration. This chapter presents swizzeling data.
DDR Data Swizzling Table 9-1. Pin Name Pin # MC Pin Name SA_DQ[0] AJ3 DQ01 SA_DQ[1] AJ4 DQ02 SA_DQ[10] AR3 SA_DQ[11] AR4 SA_DQ[12] SA_DQ[13] Table 9-1.
DDR Data Swizzling Table 9-2. Pin Name DDR Data Swizzling Table – Channle B Pin # MC Pin Name SB_DQ[0] AG7 DQ03 SB_DQ[1] AG8 DQ02 Table 9-2.
DDR Data Swizzling 110 Datasheet, Volume 1
