Intel® Xeon® Processor E5-1600/E52600/E5-4600 v2 Product Families Datasheet - Volume One of Two March 2014 Reference Number: 329187-003
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Table of Contents 1 Overview ................................................................................................................. 11 1.1 Introduction ..................................................................................................... 11 1.1.1 Processor Feature Details ........................................................................ 16 1.1.2 Supported Technologies .......................................................................... 16 1.2 Interfaces .............
3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.2.3 AES Instructions .....................................................................................84 3.2.4 Execute Disable Bit .................................................................................85 Intel® Secure Key..............................................................................................85 Intel® OS Guard ................................................................................................
6.9 6.10 Processor Asynchronous Sideband and Miscellaneous Signals ................................ 126 Processor Power and Ground Supplies ................................................................ 129 7 Electrical Specifications ......................................................................................... 131 7.1 Processor Signaling ......................................................................................... 131 7.1.1 System Memory Interface Signal Groups ................
10.3 10.4 Fan Power Supply [STS200C] ............................................................................ 232 10.3.1 Boxed Processor Cooling Requirements.................................................... 233 Boxed Processor Contents.................................................................................
2-40 2-41 2-42 2-43 2-44 2-45 2-46 2-47 2-48 2-49 2-50 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 9-1 9-2 9-3 9-4 9-5 9-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 Caching Agent TOR Read Data ............................................................................ 62 DTS Thermal Margin Read .................................................................................. 62 Processor ID Construction Example.........................................
Tables 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 8 HCC, MCC, and LCC SKU Table Summary ..............................................................11 Volume Structure and Scope ...............................................................................14 Summary of Processor-specific PECI Commands .......................................
6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-16 6-15 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 8-1 8-2 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 Intel QPI Port 0 and 1 Signals ........................................................................... 126 Intel QPI Miscellaneous Signals ......................................................................... 126 PECI Signals ...............................................................................
Revision History Revision Number 001 Description • Initial Release • • Added Intel® Xeon® Processor E5-4600 Product Family Added PPIN Feature (Protected Processor Inventory Number (PPIN): Section 1.1.1 and Table 1-6 SKU clarifications to these Sections and Tables — Updated Section 1.1.1 — Updated Table 1-2 - HCC, MCC, and LCC SKU Table Summary — Updated Section 1.
Overview 1 Overview 1.1 Introduction The Intel® Xeon® processor E5-1600/E5-2600/E5-4600 v2 product families - Volume One provides DC electrical specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. This document is intended to be distributed as a part of the complete document which consists of 2 volumes. The structure and scope of the 2 volumes are provided in Table 1-2.
Overview Table 1-1.
Overview These processors feature per socket, two Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40 lanes of PCI Express* 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space.
Overview Table 1-2.
Overview DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 Intel Xeon Processor E5-2600 v2 Product Family on the 2 Socket Platform DDR3 Figure 1-2. ethernet Intel QPI Processor SATA Processor “Legacy” . . .
Overview 1.1.1 Processor Feature Details • Up to 12 execution cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 24 threads per socket • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core • Up ot 0 3 MB last level cache (LLC): up to 2.
Overview 1.2 Interfaces 1.2.
Overview — Error reporting via Machine Check Architecture — Read Retry during CRC error handling checks by iMC — Channel mirroring within a socket — Channel Mirroring mode is supported on memory channels 0 & 1 and channels 2 & 3 — Error Containment Recovery • Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT) • Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{01/23}_N 1.2.
Overview • Supports receiving and decoding 64 bits of address from PCI Express*. — Memory transactions received from PCI Express* that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated HPA (Host Physical Address) address) are reported as errors by the processor. — Outbound access to PCI Express* will always have address bits 63 to 46 cleared.
Overview • The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2 • Operates at PCI Express* 1.0 or 2.0 speeds • Transparent to software • Processor and peer-to-peer writes and reads with 64-bit address support • APIC and Message Signaled Interrupt (MSI)support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor.
Overview • Services include CPU thermal and estimated power information, control functions for power limiting, P-state and T-state control, and access for Machine Check Architecture registers and PCI configuration space (both within the processor package and downstream devices) • PECI address determined by SOCKET_ID configuration • Single domain (Domain 0) is supported 1.3 Power Management Support 1.3.
Overview • New Memory Thermal Throttling features via MEM_HOT_C{01/23}_N signals • Running Average Power Limit (RAPL), Processor and DRAM Thermal and Power Optimization Capabilities 1.5 Package Summary The processor socket type is 52.5 x 45 mm or 52.5 x 51 mm FCLGA12 package (LGA2011-0). 1.6 Terminology Term ASPM Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core.
Overview Term ® Description ® Intel Turbo Boost Technology Intel Turbo Boost Technology is a way to automatically run the processor core faster than the marked frequency if the part is operating under power, temperature, and current specifications limits of the Thermal Design Power (TDP). This results in increased performance of both single and multithreaded applications.
Overview Term Description Phit Physical Unit. An Intel QPI terminology defining units of transfer at the physical layer. 1 Phit is equal to 20 bits in ‘full width mode’ and 10 bits in ‘half width mode’ Processor The 64-bit, single-core or multi-core component (package) Processor Core The term “processor core” refers to silicon die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache.
Overview Term 1.7 Description x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes Related Documents Refer to the following documents for additional information. 1.8 Statement of Volatility (SOV) Intel® Xeon® processor E5-1600/E5-2600/E5-4600 v2 product families do not retain any end-user data when powered down and/or the processor is physically removed from the socket. 1.
Overview 26 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. the 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels with 8 bits of ECC for each channel (total of 72-bits) and supports 1 to 3 DIMMs per channel depending on the type of memory installed.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
Interfaces Figure 2-2. Packet Flow through the Layers Framing Sequence Number Header Date ECRC LCRC Framing Transaction Layer Data Link Layer Physical Layer 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events.
Interfaces PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express* configuration space is divided into a PCI-compatible region (which consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express* region (which consists of the remaining configuration space).
Interfaces The Intel QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture.
Interfaces Generic PECI specification details are out of the scope of this document. What follows is a processor-specific PECI client definition, and is largely an addendum to the PECI Network Layer and Design Recommendations sections for the PECI specification. Note: The PECI commands described in this document apply primarily to the Intel® Xeon® processor E5-1600 v2/E5-2600 v2/E5-4600 v2 product families.
Interfaces 2.5.1.2 Platform Manageability PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices. Details are covered in subsequent sections. PECI permits writes to certain Memory Controller RAS-related registers in the processor PCI configuration space. Details are covered in Section 2.5.2.10. 2.5.
Interfaces 2.5.2.2.1 Command Format The GetDIB() format is as follows: Write Length: 0x01 Read Length: 0x08 Command: 0xf7 Figure 2-5. GetDIB() Byte # Byte Definition 2.5.2.2.2 0 1 2 3 4 Client Address Write Length 0x01 Read Length 0x08 Cmd Code 0xf7 FCS 5 6 7 8 9 Device Info Revision Number Reserved Reserved Reserved 10 11 12 13 Reserved Reserved Reserved FCS Device Info The Device Info byte gives details regarding the PECI client configuration.
Interfaces always maps to the revision number of the PECI specification that the PECI client processor is designed to. The ‘Minor Revision’ number value depends on the exact command suite supported by the PECI client as defined in Table 2-2. Figure 2-7. Revision Number Definition Byte# 6 7 4 3 0 Major Revision# Minor Revision# Table 2-2.
Interfaces 2.5.2.3.1 Command Format The GetTemp() format is as follows: Write Length: 0x01 Read Length: 0x02 Command: 0x01 Description: Returns the highest die temperature for addressed processor PECI client. Figure 2-8.
Interfaces 2.5.2.4 RdPkgConfig() The RdPkgConfig() command provides read access to the package configuration space (PCS) within the processor, including various power and thermal management functions. Typical PCS read services supported by the processor may include access to temperature data, energy status, run time information, DIMM temperatures and so on. Refer to Section 2.5.2.6 for more details on processor-specific services supported through this command. 2.5.2.4.
Interfaces 2.5.2.4.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-4. RdPkgConfig() Response Definition Response Bad Write FCS 2.5.2.5 Meaning Electrical error Abort FCS Illegal command formatting (mismatched RL/WL/Command Code) CC: 0x40 Command passed, data is valid. CC: 0x80 Response timeout.
Interfaces 2.5.2.5.1 Command Format The WrPkgConfig() format is as follows: Write Length: 0x0a(dword) Read Length: 0x01 Command: 0xa5 AW FCS Support: Yes Description: Writes data to the processor PCS entry as specified by the ‘index’ and ‘parameter’ fields. This command supports only dword data writes on the processor PECI clients. All command responses include a completion code that provides additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes.
Interfaces 2.5.2.5.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-5. WrPkgConfig() Response Definition Response Bad Write FCS 2.5.2.6 Meaning Electrical error or AW FCS failure Abort FCS Illegal command formatting (mismatched RL/WL/Command Code) CC: 0x40 Command passed, data is valid. CC: 0x80 Response timeout.
Interfaces Table 2-6.
Interfaces Table 2-6.
Interfaces 2.5.2.6.3 DRAM Rank Temperature Write This feature allows the PECI host to program into the processor, the temperature for all the ranks within a DIMM up to a maximum of four ranks as shown in Figure 2-13. The DIMM index and Channel index are specified through the parameter field as shown in Table 2-7.
Interfaces Figure 2-14. The Processor DIMM Temperature Read / Write 31 24 23 Reserved 16 15 DIMM# 2 Absolute Temp (in Degrees C) 8 7 DIMM# 1 Absolute Temp (in Degrees C) 0 DIMM# 0 Absolute Temp (in Degrees C) DIMM Temperature Data 15 3 Reserved 2 0 Channel Index Parameter format 2.5.2.6.5 DIMM Ambient Temperature Write / Read This feature allows the PECI host to provide an ambient temperature reference to be used by the processor for activity-based DRAM temperature estimation.
Interfaces Figure 2-16. Processor DRAM Channel Temperature 31 24 23 Channel 3 Maximum Temperature (in Degrees C) 16 15 Channel 2 Maximum Temperature (in Degrees C) 8 7 Channel 1 Maximum Temperature (in Degrees C) 0 Channel 0 Maximum Temperature (in Degrees C) Channel Temperature Data 2.5.2.6.7 Accumulated DRAM Energy Read This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs within all the channels or all the DIMMs within just a specified channel.
Interfaces The minimum DRAM power in Figure 2-18 corresponds to a minimum bandwidth setting of the memory interface. It does ‘not’ correspond to a processor IDLE or memory self-refresh state. The ‘time window’ in Figure 2-18 is representative of the rate at which the power control unit (PCU) samples the DRAM energy consumption information and reactively takes the necessary measures to meet the imposed power limits.
Interfaces The following conversion formula should be used for encoding or programming the ‘Control Time Window’ in bits [23:17]. Control Time Window (in seconds) = ([1 + 0.25 * ‘x’] * 2‘y’) * ‘z’ where ‘x’ = integer value of bits[23:22] ‘y’ = integer value of bits[21:17] ‘z’ = Package Power SKU Time Unit[19:16] (see Section 2.5.2.6.13 for details on Package Power SKU Unit) For example, using this formula, a control time value of 0x0A will correspond to a ‘1-second’ time window.
Interfaces 2.5.2.6.11 CPU Thermal and Power Optimization Capabilities Table 2-8 provides a summary of the processor power and thermal optimization capabilities that can be accessed over PECI. The Index values referenced in Table 2-8 are in decimal format. Note: Table 2-8 also provides information on alternate inband mechanisms to access similar or equivalent information for register reads and writes where applicable.
Interfaces Table 2-8. Service RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 2 of 4) Index Value (decimal) Parameter RdPkgConfig() WrPkgConfig Value Data () (word) (dword) Data (dword) Description Alternate Inband MSR or CSR Access “Wake on PECI” Mode bit Write / Read 05 0x0000 “Wake on PECI” mode bit N/A Read status of “Wake on PECI” mode bit Accumulated Run Time Read 31 0x0000 Total reference time N/A Returns the total run time.
Interfaces Table 2-8.
Interfaces Table 2-8.
Interfaces Figure 2-22. Platform ID Data 31 3 2 0 Processor Flag Reserved Platform ID Data • PCU Device ID: This information can be used to uniquely identify the processor power control unit (PCU) device when combined with the Vendor Identification register content and remains constant across all SKUs. Refer to the register description for the exact processor PCU Device ID value. Figure 2-23.
Interfaces Figure 2-26. Machine Check Status 31 30 CATERR IERR 29 28 0 MCERR Reserved MCA Error Source Log 2.5.2.6.13 Package Power SKU Unit Read This feature enables the PECI host to read the units of time, energy and power used in the processor and DRAM power control registers for calculating power and timing parameters. In Figure 2-27, the default value of the power unit field [3:0] is 0011b, energy unit [12:8] is 10000b and the time unit [19:16] is 1010b.
Interfaces The ‘maximum time window’ in bits [54:48] is representative of the maximum rate at which the power control unit (PCU) can sample the package energy consumption and reactively take the necessary measures to meet the imposed power limits. Programming too large a time window runs the risk of the PCU not being able to monitor and take timely action on package energy excursions.
Interfaces 2.5.2.6.17 Package Temperature Read This read returns the maximum processor die temperature in 16-bit PECI format. The upper 16 bits of the response data are reserved. The PECI temperature data returned by this read is an exponential moving average of the maximum sensor temperature (max(core and uncore sensors)), updated once every ms.
Interfaces Figure 2-30. Temperature Target Read 2.5.2.6.20 Package Thermal Status Read / Clear The Thermal Status Read provides information on package level thermal status. Data includes: • Thermal Control Circuit (TCC) activation • Bidirectional PROCHOT_N signal assertion • Critical emperature T Both status and sticky log bits are managed in this status word.
Interfaces Figure 2-32. Thermal Averaging Constant Write / Read 31 4 3 0 PECI Temperature Averaging Constant RESERVED Thermal Averaging Constant 2.5.2.6.22 Thermally Constrained Time Read This features allows the PECI host to access the total time for which the processor has been operating in a lowered power state due to TCC activation. The returned data includes the time required to ramp back up to the original P-state target after TCC activation expires.
Interfaces Figure 2-34. Accumulated Energy Read Data 0 31 Accumulated CPU Energy Accumulated Energy Status 2.5.2.6.25 Power Limit for the VCC Power Plane Write / Read This feature allows the PECI host to program the power limit over a specified time or control window for the processor logic supplied by the VCC power plane. This typically includes all the cores, home agent and last level cache. The processor does not support power limiting on a per-core basis.
Interfaces Figure 2-35. Power Limit Data for VCC Power Plane 31 24 RESERVED 23 Control Time Window 17 16 Clamp Mode 15 14 Power Limit Enable 0 VCC Plane Power Limit VCC Power Plane Power Limit Data 2.5.2.6.26 Package Power Limits For Multiple Turbo Modes This feature allows the PECI host to program two power limit values to support multiple turbo modes. The operating systems and drivers can balance the power budget using these two limits.
Interfaces Figure 2-36. Package Turbo Power Limit Data 63 56 55 49 Control Time Window #2 RESERVED 48 Clamp Mode #2 47 46 Power Limit Enable #2 32 Power Limit # 2 Package Power Limit 2 31 24 RESERVED 23 17 Control Time Window #1 16 Clamp Mode #1 15 14 Power Limit Enable #1 0 Power Limit # 1 Package Power Limit 1 2.5.2.6.27 Package Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active power limiting modes.
Interfaces 2.5.2.6.29 ACPI P-T Notify Write & Read This feature enables the processor turbo capability when used in conjunction with the PECI package RAPL or power limit. When the BMC sets the package power limit to a value below TDP, it also determines a new corresponding turbo frequency and notifies the OS using the ‘ACPI Notify’ mechanism as supported by the _PPC or performance present capabilities object.
Interfaces Figure 2-40. Caching Agent TOR Read Data 31 0 Cbo TOR Data Read Mode (bit 11) = ‘0’ (within the Paramenter) 5 31 RESERVED 4 3 Valid 0 Core ID Read Mode (bit 11) = ‘1’ (within the Parameter) Note: 2.5.2.6.31 Reads to caching agents that are not enabled will return all zeroes. Refer to the debug handbook for details on methods to interpret the crash dump results using the Cbo TOR data shown in Figure 2-40.
Interfaces Description: Returns the data maintained in the processor IA MSR space as specified by the ‘Processor ID’ and ‘MSR Address’ fields. The Read Length dictates the desired data return size. This command supports only qword responses. All command responses are prepended with a completion code that contains additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. 2.5.2.7.
Interfaces Figure 2-43. RdIAMSR() Note: 2.5.2.7.3 The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-10. RdIAMSR() Response Definition Response Bad FCS 2.5.2.7.
Interfaces PECI access to these registers is expected only when in-band access mechanisms are not available. Table 2-11.
Interfaces 3. The PECI host must determine the total number of machine check banks and the validity of the MCi_ADDR and MCi_MISC register contents prior to issuing a read to the machine check bank similar to standard machine check architecture enumeration and accesses. 4. The information presented in Table 2-11 is applicable to the processor only.
Interfaces Figure 2-45. RdPCIConfig() Note: 2.5.2.8.2 The 4-byte PCI configuration address and read data field defined in Figure 2-45 are sent in standard PECI ordering with LSB first and MSB last. Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. The PECI client response can also vary depending on the address and data.
Interfaces completion code. Alternatively, reads to unimplemented or hidden registers may return a completion code of 0x90 indicating an invalid request. It is also possible that reads to function 0 of non-existent IIO devices issued prior to BIOS POST may return all ‘0’s with a passing completion code. PECI originators can access this space even prior to BIOS enumeration of the system buses. There is no read restriction on accesses to locked registers.
Interfaces 2.5.2.9.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. The PECI client response can also vary depending on the address and data. It will respond with a passing completion code if it successfully submits the request to the location and gets a response.
Interfaces AW FCS Support: Yes Description: Writes the data sent to the requested register address. Write Length dictates the desired write granularity. The command always returns a completion code indicating pass/fail status. Refer to Section 2.5.5.2 for details on completion codes. Figure 2-48. WrPCIConfigLocal() 0 1 2 3 Client Address Write Length {0x07, 0x08, 0x0a} Read Length 0x01 Cmd Code 0xe5 Byte # Byte Definition 5 4 Host ID[7:1] & Retry[0] 8 LSB Note: 2.5.2.10.
Interfaces Table 2-14. WrPCIConfigLocal() Response Definition (Sheet 2 of 2) 2.5.2.10.3 Response Meaning CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process the request. WrPCIConfigLocal() Capabilities On the processor PECI clients, the PECI WrPCIConfigLocal() command provides a method for programming certain integrated memory controller and IIO functions as described in Table 2-15.
Interfaces Table 2-16.
Interfaces to a different PECI addresses. Strapping the SOCKET_ID[1:0] pins results in the client addresses shown in Table 2 -17. These package strap(s) are evaluated at the assertion of PWRGOOD (as depicted in Figure 2-49). The client address may not be changed after PWRGOOD assertion, until the next power cycle on the processor. Removal of a processor from its socket or tri-stating a processor will have no impact to the remaining non-tri-stated PECI client addresses.
Interfaces 2.5.3.5 S-states The processor PECI client is always guaranteed to be operational in the S0 sleep state. • The Ping(), GetDIB(), GetTemp(), RdPkgConfig(), WrPkgConfig(), RdPCIConfigLocal() and WrPCIConfigLocal() will be fully operational in S0 and S1. Responses in S3 or deeper states are dependent on POWERGOOD assertion status. • The RdPCIConfig() and RdIAMSR() responses are guaranteed in S0 only. Behavior in S1 or deeper states is indeterminate.
Interfaces 2.5.3.7.2 Link Init Mode In cases where the socket is not one QPI hop away from the Firmware Agent socket, or a working link to the Firmware Agent socket cannot be resolved, the socket is placed in Link Init mode. The socket performs a minimal amount of internal configuration and waits for complete configuration by BIOS. 2.5.3.8 Processor Error Handling Availability of PECI services may be affected by the processor PECI client error status.
Interfaces 2.5.3.10 Enumerating PECI Client Capabilities The PECI host originator should be designed to support all optional but desirable features from all processors of interest. Each feature has a discovery method and response code that indicates availability on the destination PECI client. The first step in the enumeration process would be for the PECI host to confirm the Revision Number through the use of the GetDIB() command.
Interfaces 2.5.5 Client Responses 2.5.5.1 Abort FCS The Client responds with an Abort FCS under the following conditions: • The decoded command is not understood or not supported on this processor (this includes good command codes with bad Read Length or Write Length bytes). • Assured Write FCS (AW FCS) failure. Under most circumstances, an Assured Write failure will appear as a bad FCS.
Interfaces 2.5.6 Originator Responses The simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request. However, certain completion codes or FCS responses are indicative of an error in command encoding and a retry will not result in a different response from the client. Furthermore, the message originator must have a response policy in the event of successive failure responses. Refer to Table 2 -22 for originator response guidelines.
Interfaces Temperature readings from the processor are always negative in a 2’s complement format, and imply an offset from the processor TProchot (PECI = 0). For example, if the processor TProchot is 100°C, a PECI thermal reading of -10 implies that the processor is running at approximately 10°C below TProchot or 90°C. PECI temperature readings are not reliable at temperatures above TProchot since the processor is outside its operating range and hence, PECI temperature readings are never positive.
Interfaces 80 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two
Technologies 3 Technologies 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies 3.1.
Technologies partitions in the same operating system, or there can be multiple operating system instances running on the same system – offering benefits such as system consolidation, legacy migration, activity partitioning or security. 3.1.3.
Technologies The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an trust decision. The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software. Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment.
Technologies The architecture consists of six instructions that offer full hardware support for AES. Four instructions support the AES encryption and decryption, and the other two instructions support the AES key expansion. Together, they offer a significant increase in performance compared to pure software implementations. The AES instructions have the flexibility to support all three standard AES key lengths, all standard modes of operation, and even some nonstandard or future variants.
Technologies For more information on Intel Hyper-Threading Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm. 3.6 Intel® Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads.
Technologies 3.8 Intel® Intelligent Power Technology Intel® Intelligent Power Technology conserves power while delivering advanced powermanagement capabilities at the rack, group, and data center level. Providing the highest system-level performance per watt with “Automated Low Power States” and “Integrated Power Gates”.
Technologies • Extensibility - Intel AVX has built-in extensibility for the future vector extensions: — OS context management for vector-widths beyond 256 bits is streamlined. — Efficient instruction encoding allows unlimited functional enhancements: • Vector width support beyond 256 bits • 256-bit Vector Integer processing • Additional computational and/or data manipulation primitives.
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI tSates • System tSates • Processor Core/Package States • Integrated Memory Controller (IMC) and System Memory States • Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States • Intel QuickPath Interconnect States 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State 4.1.
Power Management Table 4-2.
Power Management Table 4-4. System Memory Power States (Sheet 2 of 2) State Self-Refresh Description CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. • IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. • PLL Off: Option that sets the PLL off when self refresh occurs.
Power Management 4.2 Processor Core/Package Power Management While executing code, Enhanced Intel SpeedStep® Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies. 4.2.
Power Management Figure 4-1. Idle Power Management Breakdown of the Processor Cores T h re a d 0 T h re a d 1 T h re a d 0 C o r e 0 S ta te T h re a d 1 C o r e N S ta te P r o c e s s o r P a c k a g e S t a te Figure 4-2.
Power Management from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions via I/O reads. For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS.
Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.2, “Package C1/C1E”. To operate within specification, BIOS must enable the C1E feature for all installed processors.
Power Management — The platform may allow additional power savings to be realized in the processor. • For package C-states, the processor is not required to enter C0 before entering any other C-state. The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: • If a core break event is received, the target core is activated and the break event message is forwarded to the target core.
Power Management Figure 4-3. Package C-State Entry and Exit C1 C0 C2 C3 4.2.5.1 C6 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.
Power Management 4.2.5.3 Package C2 State Package C2 state is an intermediate state which represents the point at which the system level coordination is in progress. The package cannot reach this state unless all cores are in at least C3.
Power Management 4.2.6 Package C-State Power Specifications The table below lists the processor package C-state power specifications for various processor SKUs. For details on processor SKU information, see Table 1-1, “HCC, MCC, and LCC SKU Table Summary.”. Table 4-10.
Power Management Table 4-11. Processor Package Power Pmax TDP SKUs 200 130W 1S WS (6-cores) 190 130W 1S WS (4-cores) 175 115W (12/10-cores) 180 95W (10/8-cores) 150 95W (6/4-cores) 130 80W (6/4-cores) 110 70W (10-cores) 120 60W (6-cores) 100 LV95W (10-cores) 150 LV70W (10/8-cores) 120 LV50W (6-cores) 4.3 Pmax (W) 130W 1S WS (8-cores) 75 System Memory Power Management The DDR3 power states can be summarized as the following: • Normal operation (highest power consumption).
Power Management Difference from the active power-down mode is that when waking up all pagebuffers are empty. • Precharge power-down slow exit: In this mode the data-in DLL’s on DDR are off. Existing this mode is 3 - 5 DCLK cycles until the first command is allowed, but about 16 cycles until first data is allowed. 4.3.2 Self Refresh The Power Control Unit (PCU) may request the memory controller to place the DRAMs in self refresh state. Self refresh per channel is supported.
Power Management The I/O buffer for an unused signal should be tristated (output driver disabled), the input receiver (differential sense-amp) should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled). 4.4 DMI2/PCI Express* Power Management Active State Power Management (ASPM) support using L1 state, L0s is not supported.
Thermal Management Specifications 5 Thermal Management Specifications 5.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system, see section Section 7.7.1, “Storage Condition Specifications”. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Management Specifications The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT_N (see Section 7, “Electrical Specifications”). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications.
Thermal Management Specifications 5.1.2 TCASE and DTS Based Thermal Specifications To simplify compliance to thermal specifications at processor run time, the processor has added a Digital Thermal Sensor (DTS) based thermal specification. Digital Thermal Sensor reports a relative die temperature as an offset from TCC activation temperature. TCASE thermal based specifications are used for heat sink sizing and DTS based specs are used for acoustic and fan speed optimizations.
Thermal Management Specifications 5.1.3 Processor Operational Thermal Specifications Each SKU has a unique thermal profile that ensures reliable operation for the intended form factor over the processor’s service life. These specifications are based on final silicon characterization. The 130W 1S WS SKUs, which are part of the Intel® Xeon® processor E5-1600 v2 product family, are intended for single processor workstations and utilize workstation specific use conditions for reliability assumptions.
Thermal Management Specifications Table 5-1. TCase Temperature Thermal Specifications TDP (W) Model Number Core Count TLA (°C) PSICA (°C/W) Minimum TCASE (°C) Maximum TCASE (°C) 150W WS E5-2687W v2 8 39.5 0.217 5.0 72.0 130W 1U E5-2697 v2 12 56.5 0.227 5.0 86.0 130W 2U 130W 1S WS E5-2690 v2 10 56.5 0.242 5.0 88.0 E5-4627 v2 8 56.5 0.242 5.0 88.0 E5-2667 v2 8 49.8 0.186 5.0 74.0 E5-2643 v2 6 E5-2637 v2 4 50.1 0.199 5.0 76.0 E5-1680 v2 8 53.5 0.242 5.
Thermal Management Specifications Figure 5-1. TCase Temperature Thermal Profile 5.1.3.3 Digital Thermal Sensor (DTS) thermal profiles Each DTS thermal profile is unique to each TDP and core count combination. These TDTS profiles are fully defined by the simple linear equation: TDTS = PSIPA * P + TLA Where: PSIPA is the Processor-to-Ambient thermal resistance of the processor thermal solution. TLA is the Local Ambient temperature. P is the processor power dissipation.
Thermal Management Specifications Table 5-2. Digital Thermal Sensor (DTS) Specification Summary (Sheet 2 of 2) TDP (W) 130W 2U 130W 1S WS 115W 1U 95W 1U Model Number Core Count TLA (°C) PSIPA(°C/W) Maximum TDTS (°C) E5-2667 v2 8 49.8 0.317 91.0 E5-2643 v2 6 49.8 0.359 96.5 E5-2637 v2 4 50.1 0.422 105.0 E5-1680 v2 8 53.5 0.373 102.0 E5-1660 v2 E5-1650 v2 6 42.6 0.400 94.6 E5-1620 v2 4 42.6 0.480 105.0 E5-2695 v2 E5-4657L v2 12 55.0 0.317 91.
Thermal Management Specifications Figure 5-2. Digital Thermal Sensor DTS Thermal Profile 5.1.4 Embedded Server Thermal Profiles Network Equipment Building System (NEBS) is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. Embedded server SKU’s target operation at higher case temperatures and/or NEBS thermal profiles for embedded communications server and storage form factors.
Thermal Management Specifications Power specifications are defined at all VID values found in Table 7 -3. The processor may be delivered under multiple VIDs for each frequency. Implementation of a specified thermal profile should result in virtually no TCC activation. Failure to comply with the specified thermal profile will result in increased probability of TCC activation and may incur measurable performance loss.
Thermal Management Specifications Figure 5-3. Embedded Case Temperature Thermal Profile 5.1.4.2 Embedded Digital Thermal Sensor (DTS) thermal profiles The thermal solution is expected to be developed in accordance with the Tcase thermal profile. Operational compliance monitoring of thermal specifications and fan speed modulation may be done via the DTS based thermal profile. Each DTS thermal profile is unique to each TDP and core count combination.
Thermal Management Specifications profile graph of Figure 5-4. As a further simplification, operation at DTS temperatures up to Tcontrol is permitted at all power levels. Compliance to the DTS profile is required for any temperatures exceeding Tcontrol. Table 5-4. Embedded DTS Thermal Specifications TDP (W) Model Number Core Count TLA (°C) TLA-ST (°C) PSIPA (°C/W) Nominal Maximum TDTS (°C) Short-Term Maximum TDTS (°C) LV95W E5-2658 v2 10 51 66 0.336 82.9 97.
Thermal Management Specifications Figure 5-5. Case Temperature (TCASE) Measurement Location Notes: 1. Figure is not to scale and is for reference only. 2. This is an example for package size 52.5 x 45 mm. 3. B1: Max = 52.57 mm, Min = 52.43 mm. 4. B2: Max = 45.07 mm, Min = 44.93 mm. 5. C1: Max = 43.1 mm, Min = 42.9 mm. 6. C2: Max = 42.6 mm, Min = 42.4 mm. 7. C3: Max = 2.35 mm, Min = 2.15 mm. 5.2 Processor Core Thermal Features 5.2.
Thermal Management Specifications reduced frequency and voltage results in a reduction to the processor power consumption. The second method (clock modulation) reduces power consumption by modulating (starting and stopping) the internal processor core clocks. The processor intelligently selects the TCC method to use on a dynamic basis. BIOS is not required to select a specific method. The Adaptive Thermal Monitor feature must be enabled for the processor to be operating within specifications.
Thermal Management Specifications 5.2.2.1 Frequency/SVID Control The processor uses Frequency/SVID control whereby TCC activation causes the processor to adjust its operating frequency (via the core ratio multiplier) and VCC input voltage (via the SVID signals). This combination of reduced frequency and voltage results in a reduction to the processor power consumption. This method includes multiple operating points, each consisting of a specific operating frequency and voltage.
Thermal Management Specifications Figure 5-6. Frequency and Voltage Ordering 5.2.2.2 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor (factory configured to 37.5% on and 62.5% off for TM1). The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency.
Thermal Management Specifications increments. On-Demand mode may be used in conjunction with the Adaptive Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 5.2.4 PROCHOT_N Signal An external signal, PROCHOT_N (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature.
Thermal Management Specifications 5.2.6 Integrated Memory Controller (IMC) Thermal Features 5.2.6.1 DRAM Throttling Options The Integrated Memory Controller (IMC) has two, independent mechanisms that cause system memory throttling: • Open Loop Thermal Throttling (OLTT) and Hybrid OLTT (OLTT_Hybrid) • Closed Loop Thermal Throttling (CLTT) and Hybrid CLTT (CLTT_Hybrid) 5.2.6.1.
Thermal Management Specifications are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI threshold settings in the iMC. In Level mode, when asserted, the signal indicates to the platform that a BIOS-configured thermal threshold has been reached by one or more DIMMs in the covered channel pair. 5.2.6.
Signal Descriptions 6 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. 6.1 System Memory Interface Signals Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3 Signal Name DDR{0/1/2/3}_BA[2:0] Description Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. DDR{0/1/2/3}_CAS_N Column Address Strobe.
Signal Descriptions Table 6-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C01 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2) Signal Name Table 6-5. Description PE2D_RX_DN[15:12] PE2D_RX_DP[15:12] PCIe Receive Data Input PE2A_TX_DN[3:0] PE2A_TX_DP[3:0] PCIe Transmit Data Output PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PCIe Transmit Data Output PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PCIe Transmit Data Output PE2D_TX_DN[15:12] PE2D_TX_DP[15:12] PCIe Transmit Data Output PCI Express* Port 3 Signals Signal Name Table 6-6.
Signal Descriptions Table 6-6. PCI Express* Miscellaneous Signals (Sheet 2 of 2) Signal Name Description PCI Express* Hot-Plug SMBus Data: Provides PCI Express* hotplug support via a dedicated SMBus interface. Requires an external general purpose input/output (GPIO) expansion device on the platform. PEHPSDA 6.3 DMI2/PCI Express* Port 0 Signals Table 6-7.
Signal Descriptions 6.5 PECI Signal Table 6-10. PECI Signals Signal Name PECI 6.6 Description PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. Details regarding the PECI electrical specifications, protocols and functions can be found in the Platform Environment Control Interface Specification. System Reference Clock Signals Table 6-11.
Signal Descriptions 6.8 Serial VID Interface (SVID) Signals Table 6-13. SVID Signals SVIDALERT_N 6.9 Serial VID alert. SVIDCLK Serial VID clock. SVIDDATA Serial VID data out. Processor Asynchronous Sideband and Miscellaneous Signals Table 6-14. Processor Asynchronous Sideband Signals (Sheet 1 of 3) Signal Name Description BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable built-in self test (BIST) on the processor.
Signal Descriptions Table 6-14. Processor Asynchronous Sideband Signals (Sheet 2 of 3) Signal Name Description Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes of operation – input and output mode. MEM_HOT_C01_N MEM_HOT_C23_N Input mode is externally asserted and is used to detect external events such as VR_HOT# from the memory voltage regulator and causes the processor to throttle the memory channels. Output mode is asserted by the processor known as level mode.
Signal Descriptions Table 6-14. Processor Asynchronous Sideband Signals (Sheet 3 of 3) Signal Name Description SOCKET_ID[1:0] Socket ID Strap. Socket identification configuration straps for establishing the PECI address, Intel® QPI Node ID, and other settings. This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode).
Signal Descriptions Table 6-15. Miscellaneous Signals Signal Name 6.10 Description IVT_ID_N This output can be used by the platform to determine if the installed processor is an Intel® Xeon® processor E5-1600/E5-2600/E5-4600 v2 product families or Intel® Xeon® processor E5-1600/E5-2600/E5-4600 product families. This is pulled to ground on the processor package.This signal is also used by the VCCPLL and VTT rails to switch their output voltage to support future processors.
Signal Descriptions Table 6-16. Power and Ground Signals (Sheet 2 of 2) Signal Name Description VSA Variable power supply for the processor system agent units. These include logic (non-I/O) for the integrated I/O controller, the integrated memory controller (iMC), the Intel® QPI agent, and the Power Control Unit (PCU). The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VSA has a Vboot setting of 0.9V. Refer to the compatible VR12.
Electrical Specifications 7 Electrical Specifications 7.1 Processor Signaling The processor includes 2011 lands, which use various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Electrical Specifications 7.1.5 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 7 -17. These specifications must be met while also meeting the associated signal quality specifications outlined in Section 7.9. 7.1.6.
Electrical Specifications Table 7-1. Power and Ground Lands Power and Ground Lands 7.1.9.2 Number of Lands Comments VCCD_01 VCCD_23 51 Each VCCD land is connected to a switchable 1.50 V and 1.35 V supply, provide power to the processor DDR3 interface. These supplies also power the DDR3 memory subsystem. VCCD is also controlled by the SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23. VTTA 14 VTTA lands must be supplied by a fixed 1.0V supply.
Electrical Specifications result in as many VID transitions as necessary to reach the target voltage. Transitions above the maximum specified VID are not supported. The processor supports the following VR commands: • SetVID_fast (10 mV/µs for VSA/VCCD), • SetVID_slow 2.5 ( mV/µs for VSA/VCCD), and • Slew Rate Decay (downward voltage only and it’s a function of the output capacitance’s time constant) commands. Table 7-3 and Table 7-20 includes SVID step sizes and DC shift ranges.
Electrical Specifications • PS(01h): Represents a light load 5A to 20A • PS(02h): Represents a very light load <5A The VR may change its configuration to meet the processor’s power needs with greater efficiency. For example, it may reduce the number of active phases, transition from CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode, reduce the switching frequency or pulse skip, or change to asynchronous regulation.
Electrical Specifications Table 7-2. SVID Address Usage PWM Address (HEX) Processor 00 Vcc 01 Vsa 02 VCCD_01 03 +1 not used 04 VCCD_23 05 +1 not used Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2. VR addressing is assigned on a per voltage rail basis. 3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. 4.
Electrical Specifications Table 7-3. HEX VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2) VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD 4D 0.63000 70 0.80500 93 0.98000 B6 1.15500 D9 1.33000 FC 1.50500 4E 0.63500 71 0.81000 94 0.98500 B7 1.16000 DA 1.33500 FD 1.51000 4F 0.64000 72 0.81500 95 0.99000 B8 1.16500 DB 1.34000 FE 1.51500 50 0.64500 73 0.82000 96 0.
Electrical Specifications Table 7-4. Signal Description Buffer Types (Sheet 2 of 2) Signal PCI Express* PCI Express* interface signals. These signals are compatible with PCI Express 3.0 Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-V tolerant. Refer to the PCIe specification. Reference Voltage reference signal. SSTL Source Series Terminated Logic (JEDEC SSTL_15) 1. Table 7-5. Description Qualifier for a buffer type.
Electrical Specifications Table 7-5.
Electrical Specifications Table 7-5. Signal Groups (Sheet 3 of 3) Differential/Single Ended Signals1 Buffer Type Processor Asynchronous Sideband Signals CMOS1.0v Input BIST_ENABLE BMCINIT FRMAGENT PWRGOOD PMSYNC RESET_N SAFE_MODE_BOOT SOCKET_ID[1:0] TXT_AGENT TXT_PLTEN Open Drain CMOS Input/Output CAT_ERR_N MEM_HOT_C{01/23}_N PROCHOT_N Open Drain CMOS Output ERROR_N[2:0] THERMTRIP_N Single ended Miscellaneous Signals N/A IVT_ID_N SKTOCC_N Output Power/Other Signals 1. 2. Table 7-6.
Electrical Specifications 7.3 Power-On Configuration (POC) Options Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these options, please refer to Table 7 -7. The sampled information configures the processor for subsequent operation.
Electrical Specifications Table 7-8. 7.
Electrical Specifications 7.6 Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the processor will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not have specifications equal to the FMB value in the foreseeable future. System designers should meet the FMB values to ensure their systems will be compatible with future processors. 7.
Electrical Specifications device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality & reliability may be affected. Table 7-10. Storage Condition Ratings Symbol Parameter Min Max Unit Tabsolute storage The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time.
Electrical Specifications Table 7-11.Voltage Specification (Sheet 2 of 2) Voltage Plane Unit Notes1 mV 10 1.045*VCCPLL_TYP V 11, 12, 13, 17 1.05*VCCD_TYP V 11, 13, 14, 16, 17 1.35 1.075*VCCD_TYP V 11, 13, 14, 16, 17 0.957*VTT_TYP 1.00 1.043*VTT_TYP V 3, 5, 9, 12, 13 VSA 0.6 0.940 1.25 V 2, 3, 14, 15 VSA VSA_VID - 0.057 VSA_VID VSA_VID + 0.
Electrical Specifications Table 7-12. Processor Current Specifications Parameter Symbol and Definition Notes1 TDC (A) Max (A) ITT I/O Termination Supply, Processor Current on VTTA/VTTD 20 24 ISA System Agent Supply, Processor Current on VSA 20 24 3 4 3 4 ICCPLL PLL Supply, Processor Current on VCCPLL 2 2 ICCD_S3 Total processor current on VCCD_01/VCCD_23 in System S3 Standby State -- 0.
Electrical Specifications Table 7-13. Processor VCC Static and Transient Tolerance ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes 0 VID + 0.015 VID - 0.000 VID - 0.015 1,2,3,4,5,6 5 VID + 0.011 VID - 0.004 VID - 0.019 1,2,3,4,5,6 10 VID + 0.007 VID - 0.008 VID - 0.023 1,2,3,4,5,6 15 VID + 0.003 VID - 0.012 VID - 0.027 1,2,3,4,5,6 19 VID + 0.000 VID - 0.015 VID - 0.030 1,2,3,4,5,6 25 VID - 0.005 VID - 0.020 VID - 0.035 1,2,3,4,5,6 30 VID - 0.009 VID - 0.024 VID - 0.
Electrical Specifications 3. 4. 5. 6. Figure 7-3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_VCC_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_VCC_SENSE lands. Refer to the compatible VR12.0 PWM controller for loadline guidelines and VR implementation details. The Vcc_min and Vcc_max loadlines represent static and transient limits. Please see Section 6 for Vcc Overshoot specifications.
Electrical Specifications 7.8.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7 -14 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Figure 7-4. Load Current Versus Time Notes: 1. The peak current for any 5 second sample does not exceed Icc_max. 2.
Electrical Specifications Table 7-14. VCC Overshoot Specifications Symbol Parameter Min Max Units Figure VOS_MAX Magnitude of VCC overshoot above VID 65 mV 7-5 TOS_MAX Time duration of VCC overshoot above VccMAX value at the new lighter load 25 μs 7-5 Figure 7-5. Notes VCC Overshoot Example Waveform VOS_MAX Voltage [V] VID + VOS_MAX VccMAX (I1) TOS_MAX 0 5 10 15 20 25 30 Time [us] Notes: 1. VOS_MAX is the measured overshoot voltage. 2.
Electrical Specifications Table 7-15.
Electrical Specifications 11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the edge must be monotonic. 12. The DDR01/23_RCOMP error tolerance is ±15% from the compensated value. 13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling can be used for debug and testing purposes only. Running systems with Data Scrambling off will make the configuration out of specification.
Electrical Specifications 8. For Vin between 0 and Vih. Table 7-18. SMBus DC Specifications Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage 0.7*VTT VHysteresis Hysteresis 0.1*VTT VOL Output Low Voltage RON Buffer On Resistance IL Leakage Current Max Units 0.3*VTT V V V 0.2*VTT Output Edge Rate (50 ohm to VTT, between VIL and VIH) Notes V 4 14 Ω 50 200 μA 0.05 0.6 V/ns Table 7-19.
Electrical Specifications Table 7-20. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2) Symbol IIL Parameter Min Input Leakage Current +/-50 Input Edge Rate Signal: SVIDALERT_N 0.05 Output Edge Rate (50 ohm to VTT) 0.20 Typ Max +/-200 1.5 Units Notes μA 3,4 V/ns 5, 6 V/ns 5 Notes: 1. VTT refers to instantaneous VTT. 2. Measured at 0.31*VTT 3. Vin between 0V and VTT 4. These are measured between VIL and VIH. 5.
Electrical Specifications Table 7-22. Miscellaneous Signals DC Specifications Symbol Parameter Min Typical Max Units Notes 1.10 1.80 V 1 0 μA 1 3.50 V 1 1 mA IVT_ID_N Signal VO_ABS_MAX Output Absolute Max Voltage IO Output Current SKTOCC_N Signal VO_ABS_MAX Output Absolute Max Voltage IOMAX Output Max Current 3.30 Notes: 1. IVT_ID_N land is pulled to ground on the package. 7.8.3.
Electrical Specifications Figure 7-6. BCLK{0/1} Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 550 + 0.5 (VHavg - 700) 450 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 7-7. BCLK{0/1} Differential Clock Measurement Point for Ringback T STABLE VRB-Differential VIH = +150 mV VRB = +100 mV 0.0V VRB = -100 mV VIL = -150 mV REFCLK + Figure 7-8.
Electrical Specifications Figure 7-9. BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point BCLK_DN VCROSSDELTA = 140mV BCLK_DP 7.9 Signal Quality Data transfer requires the clean reception of data signals and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
Electrical Specifications 7.9.3 Intel® QuickPath Interconnect Signal Quality Specifications Signal Quality specifications for Differential Intel® QuickPath Interconnect Signals are included as part of the Intel QuickPath Interconnect signal quality specifications. 7.9.4 Input Reference Clock Signal Quality Specifications Overshoot/Undershoot and Ringback specifications for BCLK{0/1}_D[N/P] are found in Table 7-23.
Electrical Specifications 7.9.5.2 Overshoot/Undershoot Pulse Duration Overshoot/undershoot pulse duration describes the total amount of time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage. The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.
Electrical Specifications the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables, OR 2.
Electrical Specifications 162 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two
Processor Land Listing 8 Processor Land Listing This chapter provides sorted land list in Section 8.1 and Section 8.2. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number. 8.1 Listing by Land Name Table 8-1. Land Name (Sheet 1 of 50) Land Name Table 8-1. Land Name (Sheet 2 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 3 of 50) Table 8-1. Land No. Buffer Type Direction DDR0_DQ[10] CH4 SSTL I/O DDR0_DQ[11] CJ5 SSTL I/O Land Name (Sheet 4 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 5 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 6 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 7 of 50) Table 8-1. Land No. Buffer Type Direction DDR1_DQ[13] DB6 SSTL I/O DDR1_DQ[55] DDR1_DQ[14] DB10 SSTL I/O DDR1_DQ[56] DDR1_DQ[15] DF10 SSTL I/O DDR1_DQ[57] DDR1_DQ[16] CR7 SSTL I/O DDR1_DQ[58] Land Name (Sheet 8 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 9 of 50) Land Name Land No. Buffer Type Direction DDR1_DQS_DP[15] CP38 SSTL I/O DDR1_DQS_DP[16] DB38 SSTL I/O DDR1_DQS_DP[17] CY14 SSTL DDR1_ECC[0] DE13 SSTL DDR1_ECC[1] DF14 DDR1_ECC[2] DD16 DDR1_ECC[3] DDR1_ECC[4] Table 8-1. Land Name (Sheet 10 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 11 of 50) Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 12 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 13 of 50) Land Name Table 8-1. Land Name (Sheet 14 of 50) Land No. Buffer Type Direction Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 15 of 50) Land No. Buffer Type Direction DDR3_DQ[22] A33 SSTL I/O DDR3_DQ[23] B32 SSTL I/O DDR3_DQ[24] M32 SSTL DDR3_DQ[25] L31 SSTL DDR3_DQ[26] M28 SSTL DDR3_DQ[27] L27 SSTL DDR3_DQ[28] L33 DDR3_DQ[29] K32 Table 8-1. Land Name (Sheet 16 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 17 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 18 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 19 of 50) Land Name Land No. Buffer Type Direction Table 8-1. Land Name (Sheet 20 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 21 of 50) Land Name Table 8-1. Land Name (Sheet 22 of 50) Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 23 of 50) Land Name Table 8-1. Land Name (Sheet 24 of 50) Land No. Buffer Type Direction Land Name QPI0_DRX_DN[18] BN49 QPI I QPI0_DTX_DP[00] QPI0_DRX_DN[19] BM48 QPI I QPI0_DTX_DP[01] QPI0_DRX_DP[00] BG51 QPI I QPI0_DRX_DP[01] BF52 QPI I QPI0_DRX_DP[02] BE53 QPI QPI0_DRX_DP[03] BE55 QPI Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 25 of 50) Land Name Land No. Buffer Type Direction QPI1_DRX_DN[18] CM46 QPI I QPI1_DRX_DN[19] CN45 QPI I QPI1_DRX_DP[00] CC55 QPI I QPI1_DRX_DP[01] CD56 QPI I QPI1_DRX_DP[02] CD54 QPI QPI1_DRX_DP[03] CJ55 QPI QPI1_DRX_DP[04] CK56 QPI1_DRX_DP[05] CK54 QPI1_DRX_DP[06] QPI1_DRX_DP[07] QPI1_DRX_DP[08] QPI1_DRX_DP[09] Table 8-1. Land Name (Sheet 26 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 27 of 50) Land No. Buffer Type Table 8-1. Direction Land Name (Sheet 28 of 50) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 29 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 30 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 31 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 32 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 33 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 34 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 35 of 50) Land No. Buffer Type VSA AH16 PWR VSA AH2 PWR VSA AH4 VSA AH6 VSA VSA Table 8-1. Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 37 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 38 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 39 of 50) Land No. Buffer Type VSS BF44 GND VSS BG47 GND VSS BH58 VSS BJ55 VSS VSS VSS VSS Table 8-1. Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 41 of 50) Land No. Buffer Type Table 8-1. Direction Land Name Land Name (Sheet 42 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 43 of 50) Land No. Buffer Type VSS CN9 GND VSS CP12 GND VSS CP16 GND VSS CP36 GND VSS CP40 VSS CP42 VSS VSS Table 8-1. Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 45 of 50) Land No. Buffer Type VSS DD36 GND VSS DD38 GND VSS DD6 VSS DE17 VSS VSS Table 8-1. Direction Land Name Land Name (Sheet 46 of 50) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 47 of 50) Land No. Buffer Type VSS N49 GND VSS N5 GND VSS N53 VSS N9 VSS VSS Table 8-1. Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 49 of 50) Land Name Land No. Buffer Type VTTD AT42 PWR VTTD AY42 PWR VTTD BD42 VTTD BH42 VTTD VTTD Table 8-1. Direction Land Name (Sheet 50 of 50) Land Name Land No. Buffer Type VTTD BU47 PWR VTTD BV42 PWR PWR VTTD BY20 PWR PWR VTTD BY22 PWR BK56 PWR VTTD CA21 PWR BL51 PWR VTTD CA23 PWR VTTD BM42 PWR VTTD_SENSE BP42 VTTD BR55 PWR 8.2 Listing by Land Number Table 8-2.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 3 of 49) Table 8-2. Land Number (Sheet 4 of 49) Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 5 of 49) Land Name Buffer Type AE31 VSS GND AE33 DDR2_DQ[26] SSTL Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 7 of 49) Land Name Buffer Type Direction AH48 PE3C_RX_DN[8] PCIEX3 AH50 PE3C_RX_DN[10] PCIEX3 AH52 PE_RBIAS AH54 PE2B_TX_DP[5] AH56 AH58 Table 8-2. Land Number (Sheet 8 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 9 of 49) Direction Table 8-2. Land No. Land Number (Sheet 10 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 11 of 49) Table 8-2. Land Number (Sheet 12 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 13 of 49) Direction Table 8-2. Land No. Land Number (Sheet 14 of 49) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 15 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 17 of 49) Land No. Land Name Buffer Type Direction Table 8-2. Land Number (Sheet 18 of 49) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 19 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 21 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 23 of 49) Land No. Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 25 of 49) Land No. Land Name CF26 DDR0_CS_N[5] CF28 DDR0_ODT[3] CF30 VSS CF32 VSS CF34 CF36 Buffer Type Table 8-2. Direction Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 27 of 49) Table 8-2.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 29 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 31 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 33 of 49) Land Name Buffer Type Direction Table 8-2. Land Number (Sheet 34 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 35 of 49) Land No. Land Name Buffer Type Direction D24 DDR3_MA[14] SSTL O D26 VSS GND Table 8-2. Land Number (Sheet 36 of 49) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 37 of 49) Table 8-2. Land Number (Sheet 38 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 39 of 49) Land No. Land Name E17 DDR3_ODT[2] SSTL E19 DDR3_BA[1] SSTL E21 DDR3_MA[01] SSTL O E23 DDR3_MA[12] SSTL O 206 Buffer Type Direction Table 8-2. Land Number (Sheet 40 of 49) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 41 of 49) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 43 of 49) Table 8-2. Land Number (Sheet 44 of 49) Land No. Land Name Buffer Type Direction Land No. Land Name K6 DDR3_DQS_DP[06] SSTL I/O M30 DDR3_DQS_DN[12] SSTL I/O K8 VSS GND M32 DDR3_DQ[24] SSTL I/O L1 DDR3_DQ[62] SSTL I/O M34 VSS GND L11 DDR3_DQS_DN[05] SSTL I/O M36 VSS GND 208 Buffer Type Direction L13 DDR3_DQ[41] SSTL I/O M38 DDR3_DQS_DP[10] SSTL I/O L15 DRAM_PWR_OK_C23 CMOS1.
Processor Land Listing Table 8-2. Land Number (Sheet 45 of 49) Table 8-2. Land Number (Sheet 46 of 49) Land No. Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land No. 210 Land Number (Sheet 47 of 49) Land Name Table 8-2. Land Number (Sheet 48 of 49) Buffer Type Direction Land No.
Processor Land Listing Table 8-2. Land No.
Processor Land Listing 212 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two
Package Mechanical Specifications 9 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FCLGA12) package that interfaces with the baseboard via an LGA2011-0 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Table 9-1. Processor Package Sizes Package Size and Processor TDP SKU Notes Package A: MCC and LCC die size 52.5 mm x 45 mm (Figure 9-2 and Figure 9-3) 150W (8-core) 130W 1U (10/8-core) 130W 2U (8/6/4-core) 130W 1S WS (8/6/4-core) 115W (10-core) 95W (10/8/6/4-core) 80W (6/4-core) 70W (10-core) 60W (6-core) LV95W-10C LV70W-10C and LV70W-8C LV50W-6C Package B: HCC die size 52.5 mm x 51 mm (Figure 9-4 and Figure 9-5) 130W (12-core) 115W (12-core) 95W (8-core) 9.
Package Mechanical Specifications Figure 9-2. Processor PMD Package A (52.
Package Mechanical Specifications Figure 9-3. Processor PMD Package A (52.
Package Mechanical Specifications Figure 9-4. Processor PMD Package B (52.
Package Mechanical Specifications Figure 9-5. Processor PMD Package B (52.
Package Mechanical Specifications 9.3 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 9-3 through Figure 9-4 for keep-out zones.
Package Mechanical Specifications 9.7 Processor Mass Specification The typical mass of the processor is currently 45 grams. This mass [weight] includes all the components that are included in the package. 9.8 Processor Materials Table 9 -4 lists some of the package components and associated materials. Table 9-4. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Halogen Free, Fiber Reinforced Resin Substrate Lands 9.
Boxed Processor Specifications 10 Boxed Processor Specifications 10.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon® processor E52600 v2 and E5-4600 v2 product families (LGA2011-0) processors will be offered as Intel boxed processors, however the thermal solutions will be sold separately. Boxed processors will not include a thermal solution in the box.
Boxed Processor Specifications Figure 10-1. STS200C Passive/Active Combination Heat Sink (with Removable Fan) Figure 10-2. STS200C Passive/Active Combination Heat Sink (with Fan Removed) The STS200C utilizes a fan capable of 4-pin pulse width modulated (PWM) control. Use of a 4-pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the baseboard’s ability to directly control the RPM of the processor heat sink fan. See Section 10.
Boxed Processor Specifications sink solutions. The retention solution used for the STS200P Heat Sink Solution is called the ILM Retention System (ILM-RS).The retention solution used for the STS200PNRW Narrow Heat Sink Solution is called the Narrow ILM Retention System (Narrow ILM-RS). Figure 10-3. STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks 10.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution. 10.2.
A B C D 8 7 6 8 7 BALL 1 CORNER POSITIONAL MARKING (FOR REFERENCE ONLY) 93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE 2X FINGER ACCESS 8 6 (51.0 ) SOCKET BODY OUTLINE (FOR REFERENCE ONLY) 2X 46.0 SOCKET ILM HOLE PATTERN 93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE (FINGER ACCESS NOT INCLUDED) THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two A B C D 8 7 6 8 (93.0 ) A 2X 7.05 SEE DETAIL 2X 8.80 7 (93.0 ) 12.80 6 AS VIEWED FROM PRIMARY SIDE OF MAINBOARD 2X 3.45 2X 41.46 2X 53.808 2X 92.0 18.20 2X 31.55 2X 3.30 2X 4.50 5 5 SEE DETAIL 2X 25.25 THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION.
A B C D 8 7 6 8 7 2X 5.0 4X R7.0 22.37 4.8 4X NO ROUTE ZONE THRU ALL LAYERS 6 5 R1.00 TYP 5 AS VIEWED FROM SECONDARY SIDE OF MAINBOARD 2X 23.40 14.0 71.5 THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. 4 4 2X 26.50 81.5 3 PTMI DEPARTMENT 3 R G11950 SHT. 3 REV B 2200 MISSION COLLEGE BLVD. P.O.
8 7 6 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two A B 8 7 TOP SURFACE OF MOTHERBOARD 81.50 4.38 6 97.0° MIN 93.00 97.0° MIN 5 76.50 R 2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119 DWG. NO 2 D SHT. 4 REV SIZE DRAWING NUMBER G11950 G11950 B 1 .03 4 93.0 3 PTMI DEPARTMENT SCALE: 1.
A B C D 8 7 6 5 8 [ B 0 -0.25 +0.000 3.602 -0.009 91.50 C ] 7 +1.00 0 +0.039 -0.000 3.602 0 -0.25 +0.000 -0.009 ] 0.472 TOP VIEW [ 91.50 [ 4X 12.00 ] 6 A +1.00 0 +0.039 -0.000 0.472 ] 64.00 [2.520] MAX. AIRFLOW DIRECTION [ 4X 12.00 5 THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONT ENTS MAY NOT BE DISCLOSED, REPRODUCED, DI SPLAYED OR MODIFIED, WITHOUT THE PRI OR WRITTEN CONSENT OF INTEL CORPORAT ION.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 v2 Product Families Datasheet Volume One of Two A B C D 8 7 6 5 8 80.00 [3.150] 9 38.00 #0.50 [1.496 #0.019 ] A 7 A-A 9 80.00 [3.150] 38.00 #0.50 [1.496 #0.019 ] SECTION 6 BOTTOM VIEW FLATNESS ZONE, SEE NOTE 7 0.077 [0.0030] B SEE DETAIL 5 AIRFLOW DIRECTION A C SEE DETAIL AIRFLOW DIRECTION TOP VIEW THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION.
Boxed Processor Specifications Figure 10-10.
Boxed Processor Specifications Figure 10-11.
Boxed Processor Specifications 10.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS) Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. The standard and narrow ILM-RSs are designed to extend air-cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass. ILM-RS retention transfers load to the baseboard via the ILM Assembly.
Boxed Processor Specifications Figure 10-12.Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution Table 10-3. PWM Fan Connector Pin and Wire Description 10.3.1 Pin Number Signal Wire Color 1 Ground Black 2 Power (+12V) Yellow 3 Sense: 2 pulse per revolution Green 4 Control: 21KHz - 28KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will have three thermal solutions available. Each configuration will require unique design considerations.
Boxed Processor Specifications 10.3.1.2 STS200P and STS200PNRW (25.5mm Tall Passive Heat Sink Solution) (Blade + 1U + 2U Rack) These passive solutions are intended for use in SSI Blade, 1U or 2U rack configurations. It is assumed that a chassis duct will be implemented in all configurations. For a list processor and thermal solution boundary conditions, such as Psica, TLA, airflow, flow impedance, and so forth, see Table 10-4.
Boxed Processor Specifications Table 10-4. Server Thermal Solution Boundary Conditions (Sheet 2 of 2) TDP Thermal Solution ΨCA2 (˚C/W) TLA 1 (˚C) Airflow 3 (CFM) Delta P (inch of H2O) Heatsink Volumetric4 (mm) 95W - 10/8 Core STS200C (with fan) 0.201 55.9 Max RPM NA 91.5x91.5x64 95W - 10/8 Core STS200P 0.263 50.0 16 0.406 91.5x91.5x25.5 95W - 10/8 Core STS200PNRW 0.274 49.0 14 0.347 70x106x25.5 95W - 10/8 Core STS200C (without fan) 0.201 55.9 26 0.14 91.5x91.
Boxed Processor Specifications 10.4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below.
