Intel® Core™ i7 Processor Family for LGA2011-v3 Socket Datasheet – Volume 1 of 2 Supporting Desktop Intel® Core™ i7-5960X Extreme Edition Processor for the LGA2011-v3 Socket Supporting Desktop Intel® Core™ i7-59xx and i7-58xx Processor Series for the LGA2011-v3 Socket August 2014 330839-001
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Table of Contents 1 Introduction .............................................................................................................. 9 1.1 Processor Feature Details ................................................................................... 10 1.2 Supported Technologies ..................................................................................... 11 1.3 Interfaces ........................................................................................................ 11 1.3.
.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Direct Media Interface 2 (DMI2) Signals................................................................33 Intel® QuickPath Interconnect (Intel® QPI) Signals ................................................34 Platform Environment Control Interface (PECI) Signal .............................................34 System Reference Clock Signals ..........................................................................34 JTAG and TAP Signals.........................................
Figures 1-1 1-2 2-1 2-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 Platform Block Diagram Example ......................................................................... 10 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 13 PCI Express* Layering Diagram........................................................................... 21 Packet Flow through the Layers........................................................................... 21 Input Device Hysteresis .........
5-15 5-16 5-17 5-18 5-19 5-20 5-21 6-1 6 PECI DC Specifications .......................................................................................58 System Reference Clock (BCLK{0/1}) DC Specifications..........................................58 SMBus DC Specifications.....................................................................................60 JTAG and TAP Signals DC Specifications ................................................................
Revision History Revision Number 001 Description • Initial release Date August 2014 § Datasheet 7
Datasheet
Introduction 1 Introduction The Intel® Core™ i7 processor family for LGA2011-v3 Socket processors are the next generation of 64-bit, multi-core enterprise processors built on 22-nm process technology. Based on the low power / high performance processor microarchitecture, the processor is designed for a platform consisting of a processor and Platform Controller Hub (PCH).
Introduction Figure 1-1. Platform Block Diagram Example CH A PCI Express* 3.0 CH B Processor CH C System Memory CH D Direct Media Interface 2.0 (DMI 2.0) (x4) USB 3.0 USB 2.0 Integrated LAN Platform Controller Hub (PCH) SATA, 6 GB/s SPI Flash PCI Express* 2.0 SPI Intel® High Definition Audio (Intel® HD Audio) LPC SMBus 2.0 Super IO / EC GPIOs 1.
Introduction 1.2 Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT) Processor Extensions • Intel® 64 Architecture • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Advanced Vector Extensions 2.
Introduction 1.3.2 PCI Express* • The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.
Introduction Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) Port 0 DMI / PCIe Transaction Port 1 (IOU2) PCIe Port 2 (IOU0) PCIe Transaction Port 3 (IOU1) PCIe Transaction Transaction Link Link Link Link Physical Physical Physical Physical 0…3 0…3 4…7 0…3 4…7 8…11 12..15 0…3 4…7 8…11 12..
Introduction 1.3.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH). Refer to the Processor Thermal Mechanical Specifications and Design Guide for additional details on PECI services available in the processor (Refer to the Related Documents section).
Introduction 1.6 Package Summary The processor socket type is noted as LGA2011-v3. The processor package is a 52.5 x 45 mm FC-LGA package (LGA2011-v3). Refer to the Processor Thermal Mechanical Specification and Design Guide (see Related Documents section) for the package mechanical specifications. 1.7 Terminology Table 1-1. Terminology (Sheet 1 of 3) Term Datasheet Description ASPM Active State Power Management Cbo Caching Agent (also referred to as CA).
Introduction Table 1-1. Terminology (Sheet 2 of 3) Term Intel® 16 ME Description Intel® Management Engine Intel® QuickData Technology Intel QuickData Technology is a platform solution designed to maximize the throughput of server data traffic across a broader range of configurations and server environments to achieve faster, scalable, and more reliable I/O.
Introduction Table 1-1. Terminology (Sheet 3 of 3) Term Datasheet Description Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DDR4 DIMM. RDIMM Registered Dual In-line Memory Module RTID Request Transaction IDs are credits issued by the Cbo to track outstanding transaction, and the RTIDs allocated to a Cbo are topology dependent. SCI System Control Interrupt. Used in ACPI protocol.
Introduction 1.8 Related Documents Refer to the following documents for additional information. Table 1-2. Related Publications Document Number / Location Document Intel® Core™ i7 Processor Family for the LGA2011-v3 Socket Datasheet, Volume 2 of 2 Intel ® Core™ i7 Processor Family for the LGA2011-v3 Socket Specification Update Intel® Core™ i7 Processor Family for the LGA2011-3 Socket Thermal/Mechanical Specification and Design Guide Table 1-3.
Introduction Datasheet 19
2 Interfaces Interfaces This chapter describes the functional behaviors supported by the processor. Topics covered include: • System Memory Interface • PCI Express* Interface • Direct Media Interface 2 (DMI2) / PCI Express* Interface • Platform Environment Control Interface (PECI) 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR4 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
2.2.1.1 Interfaces Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs. 2.2.1.
Interfaces 2.3 Direct Media Interface 2 (DMI2) / PCI Express* Interface Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub (PCH). DMI2 is similar to a four-lane PCI Express* supporting a speed of 5 GT/s per lane. Note: Only DMI2 x4 configuration is supported. 2.3.1 DMI2 Error Flow DMI2 can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI2 related SERR activity is associated with Device 0. 2.3.
3 Technologies Technologies This chapter covers the following technologies: • Intel® Virtualization Technology (Intel® VT) • Security Technologies • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® Turbo Boost Technology • Enhanced Intel® SpeedStep® Technology • Intel® Advanced Vector Extensions (Intel® AVX) 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software.
Technologies 3.1.2 Intel® VT-x Features The processor core supports the following Intel VT-x features: • Extended Page Tables (EPT) — hardware assisted page table virtualization. — eliminates VM exits from guest operating system to the VMM for shadow pagetable maintenance. • Virtual Processor IDs (VPID) — Ability to assign a VM ID to tag processor core hardware structures (such as, TLBs).
3.1.3.
Technologies 3.2 Security Technologies 3.2.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Instructions These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (Intel AES-NI) which is defined by FIPS Publication number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications.
3.4 Technologies Intel® Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads. It should be enabled in the BIOS for the processor to operate with maximum performance. 3.4.
Technologies 3.6 Intel® Advanced Vector Extensions (Intel® AVX) Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel AVX started with the 2nd Generation Intel® Core™ processor family. Intel AVX accelerates the trend of parallel computation in general purpose applications like image, video and audio processing, engineering applications (such as 3D modeling and analysis), scientific simulation, and financial analysts.
Technologies • Compatibility – Intel AVX is backward compatible with previous ISA extensions including Intel SSE4: — Existing Intel SSE applications/library can: • Run unmodified and benefit from processor enhancements • Recompile existing Intel® SSE intrinsic using compilers that generate Intel AVX code • Inter-operate with library ported to Intel AVX — Applications compiled with Intel AVX can inter-operate with existing Intel SSE libraries.
Signal Descriptions 4 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. 4.1 System Memory Interface Table 4-1. Memory Channel DDR0, DDR1, DDR2, DDR3 Signal Name Datasheet Description DDR{0/1/2/3}_ACT_N Activate. When asserted, indicates MA[16:14] are command signals (RAS_N, CAS_N, WE_N). DDR{0/1/2/3}_ALERT_N Parity Error detected by the DIMM (one for each channel).
Signal Descriptions Table 4-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C01 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions Table 4-4. PCI Express* Port 2 Signals (Sheet 2 of 2) Signal Name Table 4-5. Description PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PCIe Transmit Data Output PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PCIe Transmit Data Output PE2D_TX_DN[15:12] PE2D_TX_DP[15:12] PCIe Transmit Data Output PCI Express* Port 3 Signals Signal Name Table 4-6.
Signal Descriptions 4.4 Intel® QuickPath Interconnect (Intel® QPI) Signals Table 4-8. Intel QPI Port 0 and 1 Signals Signal Name Description QPI{0/1}_CLKRX_DN/DP Reference Clock Differential Input. These pins provide the PLL reference clock differential input. 100 MHz typical. QPI{0/1}_CLKTX_DN/DP Reference Clock Differential Output. These pins provide the PLL reference clock differential input. 100 MHz typical. QPI{0/1}_DRX_DN/DP[19:0] QPI Receive data input.
Signal Descriptions Table 4-11. JTAG and TAP Signals (Sheet 2 of 2) Signal Name 4.8 Description TDO TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TMS TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRST_N TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be driven low during power on Reset. Serial VID Interface (SVID) Signals Table 4-12.
Signal Descriptions Table 4-13. Processor Asynchronous Sideband Signals (Sheet 2 of 2) Signal Name 36 Description PMSYNC Power Management Sync. A sideband signal to communicate power management status from the Platform Controller Hub (PCH) to the processor. PROCHOT_N PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature.
Signal Descriptions Table 4-14. Miscellaneous Signals (Sheet 1 of 2) Signal Name Datasheet Description BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable built-in self test (BIST) on the processor. This signal is pulled up on the die. Refer to Table 5-6, “Signals with On-Die Weak Pull-Up/Pull-Down Resistors” on page 50 for details. BMCINIT BMC Initialization Strap. Indicates whether Service Processor Boot Mode should be used.
Signal Descriptions Table 4-14. Miscellaneous Signals (Sheet 2 of 2) Signal Name 4.10 Description SOCKET_ID[1:0] Socket ID Strap. Socket identification configuration straps for establishing the PECI address, Intel® QPI Node ID, and other settings. This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode).
Electrical Specifications 5 Electrical Specifications 5.1 Integrated Voltage Regulation A new feature to the processor is the integration of platform voltage regulators into the processor. Due to this integration, the processor has one main voltage rail (VCCIN) and a voltage rail for the memory interface (VCCD01, VCCD23 – one for each memory channel pair), compared to five voltage rails (VCC, VTTA, VTTD, VSA, and VCCPLL) on previous processors.
Electrical Specifications 5.2.4 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 5-20, “Processor Asynchronous Sideband DC Specifications” on page 62. These specifications must be met while also meeting the associated signal quality specifications. 5.2.
Electrical Specifications Table 5-1. Power and Ground Lands (Sheet 2 of 2) Power and Ground Lands 5.2.8.2 Number of Lands Comments VCCIO_IN 1 IO voltage supply input VCCPECI 1 Power supply for PECI. VSS 631 Ground Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states.
Electrical Specifications • Slew Rate Decay (downward voltage only and it is a function of the output capacitance's time constant) commands. Table 5-3, “VR12.5 Reference Code Voltage Identification (VID) Table” on page 45 includes SVID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Section 5-10, “Voltage Specification” . The VRM or EVRD used must be capable of regulating its output to the value defined by the new VID.
Electrical Specifications The VR may change its configuration to meet the processor's power needs with greater efficiency. For example, it may reduce the number of active phases, transition from CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode, reduce the switching frequency or pulse skip, or change to asynchronous regulation. For example, typical power states are 00h = run in normal mode; a command of 01h = shed phases mode, and an 02h = pulse skip.
Electrical Specifications Table 5-2. SVID Address Usage (Sheet 2 of 2) PWM Address (HEX) Processor 04 VCCD_23 05 +1 not used Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2. VR addressing is assigned on a per voltage rail basis. 3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. 4.
Electrical Specifications Table 5-3. VR12.5 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2) HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN 50 1.29 73 1.64 96 1.99 B9 2.34 DC 2.69 51 1.30 74 1.65 97 2.00 BA 2.35 DD 2.70 52 1.31 75 1.66 98 2.01 BB 2.36 DE 2.71 53 1.320 76 1.67 99 2.02 BC 2.37 DF 2.72 54 1.33 77 1.68 9A 2.03 BD 2.38 E0 2.73 HEX FF VCCIN 3.04 Notes: 1. 00h = Off State 2.
Electrical Specifications Table 5-4. Signal Description Buffer Types Signal Description Analog Analog reference or output. May be used as a threshold voltage or for buffer compensation Asynchronous1 Signal has no timing relationship with any system reference clock. CMOS CMOS buffers: 1.05V DDR4 buffers: 1.2V DMI2 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 2.0 and 1.0 Signaling Environment AC Specifications. Intel® QPI Current-mode 9.6 GT/s, 8.
Electrical Specifications Table 5-5. Signal Groups (Sheet 2 of 3) Differential/Single Ended Buffer Type Signal DDR4 Miscellaneous Signals Single ended SSTL Input DDR{0/1/2/3}_ALERT_N CMOS Input Note: Input voltage from platform cannot exceed 1.08V maximum. DRAM_PWR_OK_C01 DRAM_PWR_OK_C23 CMOS 1.
Electrical Specifications Table 5-5. Signal Groups (Sheet 3 of 3) Differential/Single Ended Buffer Type Signal JTAG & TAP Signals Single ended CMOS 1.05V Input TCK TDI TMS TRST_N CMOS 1.05V Input/Output PREQ_N CMOS1.05V Output PRDY_N Open Drain CMOS Input/Output BPM_N[7:0] Open Drain CMOS Output TDO Serial VID Interface (SVID) Signals Single ended CMOS 1.
Electrical Specifications Table 5-6. Signals with On-Die Weak Pull-Up/Pull-Down Resistors Signal Name 5.
Electrical Specifications 5.5 Absolute Maximum and Minimum Ratings The following table specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications Table 5-9. Storage Condition Ratings Symbol Parameter Min Max Unit -25 125 °C Tabsolute storage The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time. Tsustained storage The minimum/maximum device storage temperature for a sustained period of time. -5 40 °C Tshort term storage The ambient storage temperature (in shipping media) for a short period of time.
Electrical Specifications Table 5-10. Voltage Specification Symbols Parameter Voltage Plane Min Nom Max Unit Notes1 VCCIN 1.47 1.8 1.85 V 2, 3, 4, 5, 9, 12 VCCIN Input to Integrated Voltage Regulator VVID_STEP (VCCIN, VCCD) VID step size during a transition – – 10.0 – mV 6 I/O Voltage for DDR4 (Standard Voltage) VCCD 0.97*VCCD_ 1.2 1.044*VC V 7, 8, 9, 10, 11 V CCD (V CCD_01, CCD_23) V NOM CD_NOM Notes: 1.
Electrical Specifications ICCIN_MAX @ VCCIN(A) ICC_ MAX @ VCCIO_ IN (A) ICC_ MAX @ VCCPECI (A) ICCD01_ MAX (A) ICCD23_ MAX (A) ICCIN_ TDC3 @ VCCIN(A) ICC_ TDC3 @ VCCIO_ IN(A) ICC_ TDC3 @ VCCPECI(A) ICCD01_ TDC (A) ICCD23_ TDC3 (A) Pmax5 @ VCCIN(W) Pmax_ Package5 (W) Notes1 High End Desktop (HEDT) 140W 8-Core 175 0.1 0.001 1.4 1.4 82 0.02 0.001 0.8 0.8 267 270 2, 4 140W 6-Core 175 0.1 0.001 1.4 1.4 82 0.02 0.001 0.8 0.8 267 270 2, 4 TDP Segment Table 5-11.
Electrical Specifications Table 5-12. VCCIN Static and Transient Tolerance Processor (Sheet 2 of 2) ICCIN (A) VCCIN_Max (V) VCCIN_Nom (V) VCCIN_Min (V) 210 VID - 0.199 VID - 0.221 VID - 0.243 220 VID - 0.209 VID - 0.231 VID - 0.253 Notes Notes: 1. The VCCIN_MIN and VCCIN_MAX loadlines represent static and transient limits. See Section 5.6.1, “Die Voltage Validation” for VCCIN Overshoot specifications. 2. This table is intended to aid in reading discrete points on graph in Figure 5-4. 3.
Electrical Specifications Table 5-13. VCCIN Overshoot Specifications Symbol Figure 5-5. Parameter Min Max Units Figure VOS_MAX Magnitude of VCCIN overshoot above VID – 50 mV 5-5 TOS_MAX Time duration of VCCIN overshoot above VCCIN_Max value at the new lighter load – 25 µs 5-5 Notes VCCIN Overshoot Example Waveform Notes: 1. VOS_MAX is the measured overshoot voltage above VCCIN_MAX. 2. TOS_MAX is the measured time duration above VCCIN_MAX. 3. VCCIN_MAX = VID + TOB 5.6.
Electrical Specifications Table 5-14.
Electrical Specifications 5.6.2.2 PECI DC Specifications Table 5-15. PECI DC Specifications Symbol Definition and Conditions Min Max Units Figure Notes1 VIn Input Voltage Range -0.150 VCCPECI + 0.150 V VHysteresis Hysteresis 0.100 * VCCPECI – V VN Negative-edge threshold voltage 0.275 * VCCPECI 0.500 * VCCPECI V 5-1 2 VP Positive-edge threshold voltage 0.550 * VCCPECI 0.725 * VCCPECI V 5-1 2 I Source Pullup Resistance (VOH = 0.75 * VCCPECI) -6.
Electrical Specifications Table 5-16. System Reference Clock (BCLK{0/1}) DC Specifications (Sheet 2 of 2) Symbol Parameter Signal Min Max Unit Figure Notes1 IIL Input Leakage Current N/A – 1.50 mA 8, 9 Cpad Pad Capacitance N/A 1.12 1.7 pF 9 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications Figure 5-8. BCLK{0/1} Single-Ended Clock Measurement Points for Absolute Cross Point and Swing Figure 5-9. BCLK{0/1} Single-Ended Clock Measure Points for Delta Cross Point 5.6.2.4 SMBus DC Specifications Table 5-17. SMBus DC Specifications Symbol Min Max Units Input Low Voltage – 0.3*V CCIO_IN V V IH Input High Voltage 0.7*VCCIO_IN – V VHysteresis Hysteresis 0.1*VCCIO_IN – V VIL Parameter V OL Output Low Voltage – 0.
Electrical Specifications 5.6.2.5 JTAG and TAP Signals DC Specifications Table 5-18. JTAG and TAP Signals DC Specifications Symbol Parameter Min Max Units VIL Input Low Voltage – 0.4*V CCIO_IN V VIH Input High Voltage 0.8*V CCIO_IN – V VIL Input Low Voltage: TCK – 0.4*VCCIO_IN V VIH Input High Voltage: TCK 0.6*VCCIO_IN – V VOL Output Low Voltage V VHysteresis Hysteresis RON Buffer On Resistance Signals BPM_N[7:0], TDO IIL – 0.2*V CCIO_IN 0.
Electrical Specifications 5.6.2.7 Processor Asynchronous Sideband DC Specifications Table 5-20. Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage – 0.4*V CCIO_IN V 1, 2 VIH_CMOS1.05V Input High Voltage 0.6*V CCIO_IN – V 1, 2 IIL_CMOS1.05V Input Leakage Current 50 200 µA 1,2 CMOS1.05v Signals VIL_CMOS1.05V Open Drain CMOS (ODCMOS) Signals VIL_ODCMOS Input Low Voltage Signals: CATERR_N, MSMI_N, PM_FAST_WAKE_N – 0.
Processor Land Listing 6 Processor Land Listing Table 6-1 provides the processor land listing organized alphabetically by signal name.
Processor Land Listing Table 6-1. 64 Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. 66 Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. 68 Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Processor Land List Processor Land List Land Number Land Name Land Number DMI_TX_DP[2] E43 PE1B_TX_DN[4] DMI_TX_DP[3] D42 PE1B_TX_DN[5] DRAM_PWR_OK_C01 CH16 DRAM_PWR_OK_C23 W29 Land Name 70 Table 6-1. Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. 72 Processor Land List Land Name Land Number QPI0_DTX_DN[14] QPI0_DTX_DN[15] Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. 74 Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. Datasheet Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1. 80 Processor Land List Table 6-1. Processor Land List Table 6-1.
Processor Land Listing Table 6-1.
Processor Land Listing 82 Datasheet
