Intel® Core™ X-Series Processor Families Datasheet – Volume 1 of 2 Supporting Intel® Core™ X-Series Processor Families – 7800X, 7820X, 7900X June 2017 335899-003
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Table of Contents 1 Introduction .............................................................................................................. 7 1.1 Processor Feature Details ..................................................................................... 8 1.2 Supported Technologies ....................................................................................... 9 1.3 Interfaces .......................................................................................................... 9 1.3.
.3 4.4 4.5 4.6 4.7 4.8 4.9 Direct Media Interface 3 (DMI3) Signals................................................................29 PECI Signal .......................................................................................................30 System Reference Clock Signals ..........................................................................30 JTAG and TAP Signals.........................................................................................30 Serial VID Interface (SVID) Signals ...
Figures 1-1 1-2 2-1 2-2 5-1 5-2 5-3 5-4 5-5 5-6 Platform Block Diagram Example ........................................................................... 8 PCI Express* Lane Partitioning and Direct Media Interface Gen 3 (DMI3) .................. 11 PCI Express* Layering Diagram........................................................................... 18 Packet Flow through the Layers........................................................................... 18 Input Device Hysteresis ....................
Revision History Revision Number Description 001 • Initial release 002 • • • • Updated Updated Updated Updated 003 • Updated Section 1.1 “Processor Feature Details” Section Section Section Section Date May 2017 1.3.1, 1.3.2, 1.4.1, 1.4.
Introduction 1 Introduction The Intel® Core™ X-Series processor families are the next generation of 64-bit, multicore processors built on 14-nm process technology. Based on the low power / high performance processor microarchitecture, the processor is designed for a platform consisting of a processor and Platform Controller Hub (PCH). The X-Series processor is used with the Intel® X299 Chipset PCH. The processor supports up to 46 bits of physical address space and 48 bits of virtual address space.
Introduction Figure 1-1. Platform Block Diagram Example CH A PCI Express* 3.0 CH B Processor CH C System Memory CH D Direct Media Interface 3.0 (DMI 3.0) (x4) USB 3.0 USB 2.0 Integrated LAN Platform Controller Hub (PCH) SATA, 6 GB/s SPI Flash PCI Express* 3.0 SPI Intel® High Definition Audio (Intel® HD Audio) LPC SMBus 2.0 Super IO / EC GPIOs 1.
Introduction 1.2 Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT) Processor Extensions • Intel® 64 Architecture • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Advanced Vector Extensions 2.
Introduction 1.3.2 PCI Express* • The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0) • Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) • Up to 44 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.
Introduction Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 3 (DMI3) Port 0 DMI / PCIe Port 1 (PE1) PCIe Port 2 (PE2) PCIe Transaction Transaction Transaction Transaction Link Link Link Link Physical Physical Physical 0..3 0..3 4..7 8..11 12..15 0..3 4..7 8..11 12..15 0..3 4..7 12..15 x4 x4 x4 x4 x4 x4 x4 x4 x4 x4 x4 x4 DMI 1.3.
Introduction • Services include processor thermal and estimated power information, control functions for power limiting, P-state and T-state control, and access for Machine Check Architecture registers and PCI configuration space (both within the processor package and downstream devices) • Single domain (Domain 0) is supported 1.4 Power Management Support 1.4.
Introduction 1.7 Terminology Table 1-1. Terminology (Sheet 1 of 3) Term Description ASPM Active State Power Management Cbo Caching Agent (also referred to as CA). It is a term used for the internal logic providing ring interface to LLC and Core. The Cbo is a functional unit in the processor. DDR4 Fourth generation Double Data Rate SDRAM memory technology. DMA Direct Memory Access DMI3 Direct Media Interface Gen2 operating at PCI Express 3.0 speed. DSB Data Stream Buffer.
Introduction Table 1-1. Terminology (Sheet 2 of 3) Term Description Intel® 14 Intel® VT-d Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or operating system) control, for enabling I/O device Virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. IOV I/O Virtualization IQ Instruction Queue.
Introduction Table 1-1. Terminology (Sheet 3 of 3) Term 1.8 Description Storage Conditions A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks.
Introduction Table 1-2. Related Documents (Sheet 2 of 2) Document Number/ Location Document PCIe* Gen 3 Connector High Speed Electrical Test Procedure 325028-001 / http://www.intel.com/ content/www/us/en/io/pciexpress/pci-expressarchitecture-devnetresources.html Connector Model Quality Assessment Methodology 326123-002 / http://www.intel.com/ content/www/us/en/ architecture-and-technology/ intel-connector-modelpaper.html DDR4 SDRAM Specification and Register Specification http://www.jedec.
Interfaces 2 Interfaces This chapter describes the functional behaviors supported by the processor. Topics covered include: • System Memory Interface • PCI Express* Interface • Direct Media Interface 3 (DMI3) / PCI Express* Interface • Platform Environment Control Interface (PECI) 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR4 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per channel. 2.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
Interfaces 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs. 2.2.1.
Interfaces 2.3 Direct Media Interface 3 (DMI3) / PCI Express* Interface Direct Media Interface 3 (DMI3) connects the processor to the Platform Controller Hub (PCH). DMI3 is similar to a four-lane PCI Express* supporting a speed of 8 GT/s per lane. Note: Only DMI3 x4 configuration is supported. 2.3.1 DMI3 Error Flow DMI3 can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI3 related SERR activity is associated with Device 0. 2.3.
Technologies 3 Technologies This chapter covers the following technologies: • Intel® Virtualization Technology (Intel® VT) • Security Technologies • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® Turbo Boost Technology • Enhanced Intel® SpeedStep® Technology • Intel® Advanced Vector Extensions (Intel® AVX) 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software.
Technologies 3.1.2 Intel® VT-x Features The processor core supports the following Intel VT-x features: • Extended Page Tables (EPT) — hardware assisted page table virtualization. — eliminates VM exits from guest operating system to the VMM for shadow pagetable maintenance. • Virtual Processor IDs (VPID) — Ability to assign a VM ID to tag processor core hardware structures (such as, TLBs).
Technologies 3.1.3.
Technologies 3.2 Security Technologies 3.2.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Instructions These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (Intel AES-NI) which is defined by FIPS Publication number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications.
Technologies 3.4 Intel® Turbo Boost Max Technology 3.0 Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads. It should be enabled in the BIOS for the processor to operate with maximum performance. Processors with Intel Turbo Boost Max Technology 3.
Technologies allows logic to remain active. The core clock can also restart more quickly under Enhanced Intel SpeedStep Technology. 3.6 Intel® Advanced Vector Extensions (Intel® AVX) Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel AVX started with the 2nd Generation Intel® Core™ processor family.
Technologies • Compatibility – Intel AVX is backward compatible with previous ISA extensions including Intel SSE4: — Existing Intel SSE applications/library can: • Run unmodified and benefit from processor enhancements • Recompile existing Intel® SSE intrinsic using compilers that generate Intel AVX code • Inter-operate with library ported to Intel AVX — Applications compiled with Intel AVX can inter-operate with existing Intel SSE libraries.
Signal Descriptions 4 Signal Descriptions This chapter describes the signals. They are arranged in functional groups according to their associated interface or category. 4.1 System Memory Interface Table 4-1. Memory Channel DDR0, DDR1, DDR2, DDR3, DDR4, DDR5 Signal Name DDR{5:0}_ACT_N Activate. When asserted, indicates MA[16:14] are command signals (RAS_N, CAS_N, WE_N). DDR{5:0}_ALERT_N Parity Error detected by the DIMM (one for each channel). DDR{5:0}_BA[1:0] Bank Address.
Signal Descriptions Table 4-2. Memory Channel Miscellaneous Signal Name Description DDR {012,345}_RESET_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR012_RESET_N is used for memory channels 0, 1 and 2 while DDR345_RESET_N is used for memory channels 3, 4 and 5. DDR{012,345}_SPDSCL SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions 4.4 PECI Signal Table 4-6. PECI Signal Signal Name Description PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. PECI 4.5 System Reference Clock Signals Table 4-7. System Reference Clock (BCLK{0/1/2}) Signals Signal Name BCLK{0,1,2}_DN/DP Description Reference Clock Differential input.
Signal Descriptions 4.7 Serial VID Interface (SVID) Signals Table 4-9. SVID Signals Signal Name SVIDALERT_N [1:0] 4.8 Description Serial VID alert. SVIDCLK [1:0] Serial VID clock. SVIDDATA [1:0] Serial VID data out. Processor Asynchronous Sideband and Miscellaneous Signals Table 4-10. Processor Asynchronous Sideband Signals (Sheet 1 of 2) Signal Name Description CATERR_N Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate.
Signal Descriptions Table 4-10. Processor Asynchronous Sideband Signals (Sheet 2 of 2) Signal Name Description PWRGOOD PWRGOOD is a processor input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Signal Descriptions Table 4-11. Miscellaneous Signals (Sheet 2 of 3) Signal Name Description EAR_N External Alignment of Reset, used to bring the processor up into a deterministic state. This signal is pulled up on the die, refer to Table 5-7, “Signals with On-Die Weak PU/PD” for details. FIVR_FAULT Indicates an internal error has occurred with the integrated voltage regulator. The FIVR_FAULT signal can be sampled any time after 1.5 ms after the assertion of PWRGOOD.
Signal Descriptions Table 4-11. Miscellaneous Signals (Sheet 3 of 3) Signal Name 4.9 Description TXT_PLTEN Intel® Trusted Execution Technology (Intel® TXT) Platform Enable Strap. 0 = The platform is not Intel® TXT enabled. All sockets should be set to zero. Scalable DP (sDP) platforms should choose this setting if the Node Controller does not support Intel® TXT. 1 = Default. The platform is Intel® TXT enabled. All sockets should be set to one. In a non-Scalable DP platform this is the default.
Electrical Specifications 5 Electrical Specifications This chapter describes processor signaling and DC specifications. References to various interfaces (memory, PCIe* PECI, and so forth) are also described. 5.1 Integrated Voltage Regulation The platform voltage regulator is integrated into the processor. Due to this integration, the processor has one main voltage rail (VCCIN) and a voltage rail for the memory interface (VCCD012, VCCD345 - one for each memory channel pair).
Electrical Specifications 5.2.4 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1/2}_DP, BCLK{0/1/2}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1/ 2}_DP, BCLK{0/1/2}_DN inputs are provided in Section 5.5.2.7. 5.2.
Electrical Specifications 5.2.8.2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Large electrolytic bulk capacitors (CBULK), help maintain the output voltage during current transients, for example coming out of an idle condition.
Electrical Specifications Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. 5.2.8.5 SetWP Working Point Command The SetWP is a command that invokes a look up table for VID set points. During the initial power on phase the CPU will program the WPx registers (WP0=3Ah..WP7=41h) on a per rail address basis.
Electrical Specifications The SetVID_Fast command is preemptive. The VR interrupts its current processes and moves to the new VID. The SetVID_Fast command operates on 1 VR address at a time. This command is used in the processor for package C6 fast exit. 5.2.8.7 SetVID Slow The SetVID_Slow command contains the target VID in the payload byte. The range of voltage is defined in the VID table. The VR should ramp to the new VID setting with a “slow” slew rate as defined in the slow slew rate data register.
Electrical Specifications Table 5-3. SVID Address Usage Bus 2 PWM Address (HEX) 00 Protocol ID 04H(10mV VID) or 07H(5mV VID) 01 Processor VCCD012 NA 02 04H(10mV VID) or 07H(5mV VID) 03 VCCD345 NA Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2. VR addressing is assigned on a per voltage rail basis. 3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. Table 5-4. VR13.
Electrical Specifications Table 5-4. VR13.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2) HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN HEX VCCIN 1E 0.79 3E 1.11 5E 1.43 7E 1.75 9E 2.07 BE 2.39 DE 2.71 FE 3.03 1F 0.80 3F 1.12 5F 1.44 7F 1.76 9F 2.08 BF 2.40 DF 2.72 FF 3.04 Notes: 1. 00h = Off State 2. VID Range HEX 65-97 are not used by the processor 3. VCCD can use Protocol ID of 10 mV or 5 mV. 4.
Electrical Specifications Table 5-6.
Electrical Specifications Table 5-6. Signal Groups (Sheet 2 of 2) Differential/Single Ended Buffer Type Signal System Reference Clock (BCLK{0/1/2}) Differential CMOS 1.
Electrical Specifications Table 5-7. Signals with On-Die Weak PU/PD Signal Name BIST_ENABLE 5.3.
Electrical Specifications Table 5-8. Power-On Configuration Option Lands (Sheet 2 of 2) Configuration Option Land Name Notes Enable Intel Trusted Execution Technology (Intel TXT) Agent TXT_AGENT 3 Enable Safe Mode Boot SAFE_MODE_BOOT 3 Configure Socket ID SOCKET_ID[1:0] 3 Enable legacy socket boot LEGACY_SKT 3 Notes: 1. Output tri-state option enables Fault Resilient Booting (FRB), for FRB details, see the Fault Resilient Booting (FRB) Section.
Electrical Specifications maximum or minimum device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality and reliability may be affected. Table 5-10. Storage Condition Ratings Symbol Tabsolute storage Parameter The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time.
Electrical Specifications Table 5-11. Voltage Specification (Sheet 2 of 2) Symbols Parameter V CCD (V CCD_012, V CCD_345) I/O Voltage for DDR4 (Standard Voltage) VCCSA Power supply for IIO VCCIO IO voltage supply input VCC33 Power supply for PIROM Voltage Plane Min Nom Max Unit VCCD 1.17 1.2 1.26 V 0.5 — 1.1 V — 0.937 1.00 1.057 V 3.14 3.3 3.47 V Notes1 7, 9, 10, 11 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. 2.
Electrical Specifications Table 5-12. Current (ICCIN_MAX and ICCIN_TDC) Specification (Sheet 2 of 2) TDP (W) 140 Pmax VCCIN (W) Pmax Package (W) 297 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. 2. N/A 3. ICCIN_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment.
Electrical Specifications Table 5-13. VCCIN Static and Transient Tolerance for 1.0LL (Sheet 2 of 2) ICCIN (A) VCCIN_Max (V) VCCIN_Nom (V) VCCIN_Min (V) 220 VID -0.198 VID -0.220 VID -0.242 230 VID - 0.208 VID - 0.230 VID - 0.252 Notes Notes: 1. The VCCIN_MIN and VCCIN_MAX loadlines represent static and transient limits. 2. This table is intended to aid in reading discrete points on graph in Figure 5-2, “VCCIN Static and Transient Tolerance Load Lines 1.0 mOHM” on page 50. 3.
Electrical Specifications Symbol Parameter Min Nom Max Units — (V CCD / 2)* (R ON / (R ON +R VTT_TERM )) — V - ((V CCD / 2)* (R ON /(R ON +R VTT_TERM ))) — V — Vol=(Ron / (Ron + RVDD_TERM)) *VCCD — V — VCCD — V DDR4 Clock Buffer On Resistance 25.5 30 34.
Electrical Specifications 5.5.2.2 Symbol PECI DC Specifications Definition and Conditions VIn Input Voltage Range Min Max Units -0.15 0.15 + VCCIO V Figure Notes1 1 VHysteresis Hysteresis 0.1*VCCIO — V VN Negative-edge threshold voltage 0.275*VCCIO 0.500*VCCIO V Figure 5-1 2 VP Positive-edge threshold voltage 0.550*VCCIO 0.725*VCCIO V Figure 5-1 2 I Pullup Resistance (VOH = 0.75*VCCIO) -6.
Electrical Specifications Symbol Parameter Signal Min Max Unit Figure Notes1 IIL Input Leakage Current N/A — 1.50 mA 8, 9 Cpad Pad Capacitance N/A 1.90 1.72 pF 9 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. 3.
Electrical Specifications Figure 5-5. BCLK{0/1/2} Single Ended Clock Measurement Points for Absolute Cross Point and Swing Figure 5-6. BCLK{0/1/2} Single Ended Clock Measure Points for Delta Cross Point 5.5.2.4 SMBus DC Specifications Symbol Parameter Min Max Units VIL Input Low Voltage — 0.3*VCCIO V V IH Input High Voltage 0.7*VCCIO — V VHysteresis Hysteresis 0.1*VCCIO — V V OL Output Low Voltage — 0.
Electrical Specifications Symbol Parameter Min Max Units IIL Input Leakage Current Signals ±50 ±200 µA SR Output Edge Rate (50 ohm to VCCIO) Signal: BPM_N[7:0], PRDY_N, TDO 1.13 5 V/ns Notes 1 Notes: 1. These are measured between VIL and VIH. 2. The signal edge rate must be met or the signal must transition monotonically to the asserted state. 5.5.2.6 Serial VID Interface (SVID) DC Specifications Symbol Parameter Min Nom Max Units VCCIO - 5% 1.
Electrical Specifications Symbol Parameter RON Buffer On Resistance SR Output Edge Rate Min Max Units 14 4 1.13 5 V/ns Notes 1, 2, 4 3, 5 Notes: 1. This table applies to the processor sideband and miscellaneous signals specified in Table 5-6, “Signal Groups”. 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 3. These are measured between VIL and VIH. 4.
