Specification Sheet

Introduction
10 Datasheet, Volume 1 of 2
1.3.2 PCI Express*
• The PCI Express* port(s) are fully-compliant with the PCI Express* Base
Specification, Revision 3.0 (PCIe* 3.0).
• Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s).
• Up to 44 lanes of PCI Express* interconnect for general purpose PCI Express*
devices at PCIe* 3.0 speeds that are configurable for up to ten independent ports:
— Intel
®
Core™ i7-7820X, i9-7900X, i9-7920X, i9-7940X, i9-7960X, i9-7980XE
processor support 44 lanes
— Intel
®
Core™ i7-9800X, i9-9820X, i9-9900X, i9-9920X, i9-9940X, i9-9960X,
i9-9980XE processor support 44 lanes
— Intel
®
Core™ i7-7800X processor supports 28 lanes
• Negotiating down to narrower widths is supported. Refer Figure 1-2.
— x16 port (Port 1 and Port 2) may negotiate down to x8, x4, x2, or x1
— x12 port (Port 3) may negotiate down to x8, x4, x2, or x1
• Address Translation Services (ATS) 1.0 support.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism – accessing the device configuration
space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Supports receiving and decoding 64 bits of address from PCI Express*:
— Memory transactions received from PCI Express* that go above the top of
physical address space (when Intel VT-d is enabled, the check would be against
the translated Host Physical Address (HPA)) are reported as errors by the
processor.
— Outbound access to PCI Express* will always have address bits 63:46 cleared
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
• Power Management Event (PME) functions.
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Degraded Mode support and Lane Reversal support.
• Static lane numbering reversal and polarity inversion support.
• Support for PCIe* 3.0 atomic operation, PCIe* 3.0 optional extension on atomic
read-modify-write mechanism.