Specification Sheet

Datasheet, Volume 1 of 2 11
Introduction
1.3.3 Direct Media Interface
• Chip-to-chip interface to the PCH.
• The DMI3 port supports x4 link width and only operates in a x4 mode when in
DMI3.
• Operates at PCI Express* 1.0, 2.0, 3.0 speeds.
• Transparent to software.
• Processor and peer-to-peer writes and reads with 64-bit address support.
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication.
• Static lane numbering reversal support.
• Supports DMI virtual channels VC0, VC1, VCm, and VCp.
Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Generation 3
(DMI3)