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Errata
Specification Update 31
KBL022
Placing an Intel® PT ToPA in Non-WB Memory or Writing It Within a
Transactional Region May Lead to System Instability
Problem
If an Intel PT (Intel® Processor Trace) ToPA (Table of Physical Addresses) is not
placed in WB (writeback) memory or is written by software executing within an
Intel® TSX (Intel® Transactional Synchronization Extension) transactional region,
the system may become unstable.
Implication Unusual treatment of the ToPA may lead to system instability.
Workaround
None identified. Intel PT ToPA should reside in WB memory and should not be written
within a Transactional Region.
Status For the steppings affected, see the Summary Table of Changes.
KBL023 VM Entry That Clears TraceEn May Generate a FUP
Problem
If VM entry clears Intel® PT (Intel Processor Trace) IA32_RTIT_CTL.TraceEn (MSR
570H, bit 0) while PacketEn is 1 then a FUP (Flow Update Packet) will precede the
TIP.PGD (Target IP Packet, Packet Generation Disable). VM entry can clear TraceEn if
the VM-entry MSR-load area includes an entry for the IA32_RTIT_CTL MSR.
Implication
When this erratum occurs, an unexpected FUP may be generated that creates the
appearance of an asynchronous event taking place immediately before or during the
VM entry.
Workaround
The Intel PT trace decoder may opt to ignore any FUP whose IP matches that of a VM
entry instruction.
Status For the steppings affected, see the Summary Table of Changes.
KBL024
Performance Monitor Event For Outstanding Offcore Requests And Snoop
Requests May be Incorrect
Problem
The performance monitor event OFFCORE_REQUESTS_OUTSTANDING (Event 60H,
any Umask Value) should count the number of offcore outstanding transactions each
cycle. Due to this erratum, the counts may be higher or lower than expected.
Implication
The performance monitor event OFFCORE_REQUESTS_OUTSTANDING may reflect an
incorrect count.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.