Other Content

Errata
34 Specification Update
KBL033
Processor DDR VREF Signals May Briefly Exceed JEDEC Spec When Entering
S3 State
Problem
Voltage glitch of up to 200mV on the VREF signal lasting for about 1mS may be
observed when entering System S3 state. This violates the JEDEC DDR specifications.
Implication
Intel has not observed this erratum to impact the operation of any commercially
available system.
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL034
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is
Followed by a Store or an MMX Instruction
Problem
Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not
cause a debug exception immediately after MOV/POP SS but will be delayed until the
instruction boundary following the next instruction is reached. After the debug
exception occurs, DR6.B0-B3 bits will contain information about data breakpoints
matched during the MOV/POP SS as well as breakpoints detected by the following
instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about
data breakpoints matched during the MOV/POP SS when the following instruction is
either an MMX instruction that uses a memory addressing mode with an index or a
store instruction.
Implication
When this erratum occurs, DR6 may not contain information about all breakpoints
matched. This erratum will not be observed under the recommended usage of the
MOV SS,r/m or POP SS instructions (i.e., following them only with an instruction that
writes (E/R)SP).
Workaround None identified.
Status For the steppings affected, see the Summary Table of Changes.
KBL035 ENCLS[EINIT] Instruction May Unexpectedly #GP
Problem
When using Intel® SGX (Software Guard Extensions), the ENCLS[EINIT] instruction
will incorrectly cause a #GP (general protection fault) if the MISCSELECT field of the
SIGSTRUCT structure is not zero.
Implication
This erratum may cause an unexpected #GP, but only if software has set bits in the
MISCSELECT field in SIGSTRUCT structure that do not correspond to extended
features that can be written to the MISC region of the SSA (State Save Area). Intel
has not observed this erratum with any commercially available software.
Workaround
When executing the ENCLS[EINIT] instruction, software should only set bits in the
MISCSELECT field in the SIGSTRUCT structure that are enumerated as 1 by
CPUID.(EAX=12H,ECX=0):EBX (the bit vector of extended features that can be
written to the MISC region of the SSA).
Status For the steppings affected, see the Summary Table of Changes.