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ManualsBrandsINTEL ManualsPC ComponentsBoxed processor Core i5 i5-7500 4 x 3.4 GHz
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Errata
Specification Update 47
KBL077 Use of VMASKMOV to Store When Using EPT May Fail
Problem
Use of VMASKMOV instructions to store data that splits over two pages, when the
instruction resides on the first page may cause a hang if EPT (Extended Page Tables)
is in use, and the store to the second page requires setting the A/D bits in the EPT
entry.
Implication Due to this erratum, the CPU may hang on the execution of VMASKMOV
Workaround It is possible for the BIOS to contain a workaround for this erratum.
Status For the steppings affected, see the Summary Table of Changes.
KBL078 PECI May Not be Functional After Package C10 Resume
Problem When resuming from Package C10, PECI may fail to function properly.
Implication When this erratum occurs, the PECI does not respond to any command.
Workaround
It is possible for BIOS to contain processor configuration data and code changes as a
workaround for this erratum.
Status For the steppings affected, see the Summary Table of Changes.
KBL079 Attempts to Retrain a PCIe* Link May be Ignored
Problem
A PCIe link should retrain when Retrain Link (bit 5) in the Link Control register (Bus
0; Device 1; Functions 0,1,2; Offset 0xB0) is set. Due to this erratum, if the link is in
the L1 state, it may ignore the retrain request
Implication The PCIe link may not behave as expected.
Workaround It is possible for the BIOS to contain a workaround for this erratum.
Status For the steppings affected, see the Summary Table of Changes.
KBL080 PCIe* Expansion ROM Base Address Register May be Incorrect
Problem
After PCIe 8.0 GT/s Link Equalization on a root port (Bus 0; Device 1; Function 0, 1,
2) has completed, the Expansion ROM Base Address Register (Offset 38H) may be
incorrect.
Implication
Software that uses this BAR may behave unexpectedly. Intel has not observed this
erratum with any commercially available software.
Workaround None identified
Status For the steppings affected, see the Summary Table of Changes.
KBL081 PCIe* Port Does Not Support DLL Link Activity Reporting
Problem
The PCIe Base specification requires DLL (Data Link Layer) Link Activity Reporting
when 8 GT/s link speed is supported. Due to this erratum, link activity reporting is
not supported
Implication
Due to this erratum, PCIe port does not support DLL Link Activity Reporting when 8
GT/s is supported.
Workaround None identified