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Errata
50 Specification Update
KBL090
Violations of Intel® Software Guard Extensions (Intel® SGX) Access-Control
Requirements Produce #GP Instead of #PF
Problem
Intel® Software Guard Extensions (Intel® SGX) define new access-control
requirements on memory accesses. A violation of any of these requirements causes a
page fault (#PF) that sets bit 15 (SGX) in the page-fault error code. Due to this
erratum, these violations instead cause general-protection exceptions (#GP).
Implication
Software resuming from system sleep states S3 or S4 and relying on receiving a page
fault from the above enclave accesses may not operate properly.
Workaround
Software can monitor #GP faults to detect that an enclave has been destroyed and
needs to be rebuilt after resuming from S3 or S4
Status For the steppings affected, see the Summary Table of Changes.
KBL091 IA32_RTIT_CR3_MATCH MSR Bits[11:5] Are Treated As Reserved
Problem
Due to this erratum, bits[11:5] in IA32_RTIT_CR3_MATCH (MSR 572H) are reserved;
an MSR write that attempts to set that field to a non-zero value will result in a #GP
fault.
Implication
The inability to write the identified bit field does not affect the functioning of Intel®
PT (Intel® Processor Trace) operation because, as described in erratum SKL061, the
bit field that is the subject of this erratum is not used during Intel PT CR3 filtering.
Workaround
Ensure that bits 11:5 of the value written to IA32_RTIT_CR3_MATCH are zero,
including cases where the selected page-directory-pointer-table base address has
non-zero bits in this range.
Status For the steppings affected, see the Summary Table of Changes.
KBL092
APIC Timer Interrupt May Not be Generated at The Correct Time In TSC-
Deadline Mode
Problem
After writing to the IA32_TSC_ADJUST MSR (3BH), any subsequent write to the
IA32_TSC_DEADLINE MSR (6E0H) may incorrectly process the desired deadline.
When this erratum occurs, the resulting timer interrupt may be generated at the
incorrect time.
Implication
When the local APIC (Advanced Programmable Interrupt Controller) timer is
configured for TSC-Deadline mode, a timer interrupt may be generated much earlier
than expected or much later than expected. Intel has not observed this erratum with
most commercially available software.
Workaround It is possible for the BIOS to contain a workaround for this erratum.
Status For the steppings affected, see the Summary Table of Changes.