Specification Sheet
Datasheet, Volume 2 of 2 133
Dynamic Power Performance Management (DPPM) Registers
5 Dynamic Power Performance
Management (DPPM) Registers
5.1 Device Enable (DEVEN)—Offset 54h
Allows for enabling/disabling of PCI devices and functions that are within the Processor
package. The table below the bit definitions describes the behavior of all combinations
of transactions to devices controlled by this register.
All the bits in this register are Intel TXT Lockable.
Access Method
Default: 84BFh
Table 5-1. Summary of Bus: 0, Device: 4, Function: 0 (CFG)
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default
Value
54–57h 4 Device Enable (DEVEN)—Offset 54h 84BFh
E4–E7h 4 Capabilities A (CAPID0)—Offset E4h 0h
E8–EBh 4 Capabilities B (CAPID0)—Offset E8h 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:4, F:0] + 54h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
RSVD
D8EN
D7EN
D6EN
RSVD
D5EN
RSVD
D4EN
RSVD
D3EN
D2EN
D1F0EN
D1F1EN
D1F2EN
D0EN
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15
1h
RO_V
D8EN:
0: Bus 0 Device 8 is disabled and not visible.
1: Bus 0 Device 8 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 8 capability is disabled.
14
0h
RO_V
D7EN:
0: Bus 0 Device 7 is disabled and not visible.
1: Bus 0 Device 7 is enabled and visible.
Non-production BIOS code should provide a setup option to enable Bus 0 Device 7.
When enabled, Bus 0 Device 7 should be initialized in accordance to standard PCI
device initialization procedures.