Specification Sheet

Datasheet, Volume 2 of 2 163
DMIBAR Registers
6.26 DMI Uncorrectable Error Status (DMIUESTS)—
Offset 1C4h
DMI Uncorrectable Error Status register. This register is for test and debug purposes
only.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 1C4h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
URES
RSVD
MTLPS
ROS
UCS
RSVD
CTS
RSVD
PTLPS
RSVD
DLPES
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:21
0h
RO
Reserved (RSVD): Reserved.
20
0h
RW1CS
URES: Unsupported Request Error Status:
19
0h
RO
Reserved (RSVD): Reserved.
18
0h
RW1CS
MTLPS: Malformed TLP Status:
17
0h
RW1CS
ROS: Receiver Overflow Status:
16
0h
RW1CS
UCS: Unexpected Completion Status:
15
0h
RO
Reserved (RSVD): Reserved.
14
0h
RW1CS
CTS: Completion Timeout Status:
13
0h
RO
Reserved (RSVD): Reserved.
12
0h
RW1CS
PTLPS: Poisoned TLP Status:
11:5
0h
RO
Reserved (RSVD): Reserved.
4
0h
RW1CS
DLPES: Data Link Protocol Error Status:
3:0
0h
RO
Reserved (RSVD): Reserved.