Specification Sheet

Datasheet, Volume 2 of 2 215
MCHBAR Registers
7.46 PKG—Offset 5828h
Sum the cycles per number of active cores
Access Method
Default: 0h
7.47 PKG—Offset 5830h
C0.Any - Sum the cycles of any active cores.
Access Method
Default: 0h
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 5828h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA
Bit
Range
Default &
Access
Field Name (ID): Description
63:0
0h
ROV
DATA: RO: The counter value is incremented as a function of the number of cores that
reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock
ticks" that are incremented is N. Counter rate is the Max Non-Turbo frequency (same
as TSC)
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 5830h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA
Bit
Range
Default &
Access
Field Name (ID): Description
63:0
0h
ROV
DATA: RO, This counter increments whenever one or more IA cores are active and in
C0 state. Counter rate is the Max Non-Turbo frequency (same as TSC)