Specification Sheet
Datasheet, Volume 2 of 2 329
VC0PREMAP Registers
10.20 Invalidation Queue Tail Register (IQT)—Offset
88h
Register indicating the invalidation tail head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:19
0h
RO
Reserved (RSVD): Reserved.
18:4
0h
ROV
QH: Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be fetched next by hardware.
Hardware resets this field to 0 whenever the queued invalidation is disabled (QIES
field Clear in the Global Status register).
3:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 88h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
QT
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
63:19
0h
RO
Reserved (RSVD): Reserved.
18:4
0h
RW_L
QT: Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be written next by software.
3:0
0h
RO
Reserved (RSVD): Reserved.