Specification Sheet
VC0PREMAP Registers
338 Datasheet, Volume 2 of 2
10.31 IOTLB Invalidate Register (IOTLB)—Offset 508h
Register to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with
IVT field Set causes the hardware to perform the IOTLB invalidation.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:12
0h
RW
ADDR: Software provides the DMA address that needs to be page-selectively
invalidated. To make a page-selective invalidation request to hardware, software
should first write the appropriate fields in this register, and then issue the appropriate
page-selective invalidate command through the IOTLB_REG. Hardware ignores bits
63 : N, where N is the maximum guest address width (MGAW) supported.
11:7
0h
RO
Reserved (RSVD): Reserved.
6
0h
RW
IH: The field provides hint to hardware about preserving or flushing the non-leaf
(page-directory) entries that may be cached in hardware:
0: Software may have modified both leaf and non-leaf page-table entries
corresponding to mappings specified in the ADDR and AM fields. On a page-selective
invalidation request, hardware should flush both the cached leaf and non-leaf page-
table entries corresponding tot he mappings specified by ADDR and AM fields.
1: Software has not modified any non-leaf page-table entries corresponding to
mappings specified in the ADDR and AM fields. On a page-selective invalidation
request, hardware may preserve the cached non-leaf page-table entries corresponding
to mappings specified by ADDR and AM fields.
5:0
0h
RW
AM: The value in this field specifies the number of low order bits of the ADDR field that
should be masked for the invalidation operation. This field enables software to request
invalidation of contiguous mappings for size-aligned regions. For example:
Mask ADDR bits Pages
Value masked invalidated
0 None 1
1 12 2
2 13:12 4
3 14:12 8
4 15:12 16
... ....... .....
When invalidating mappings for super-pages, software should specify the appropriate
mask value. For example, when invalidating mapping for a 2MB page, software should
specify an address mask value of at least 9.
Hardware implementations report the maximum supported mask value through the
Capability register.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 508h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IVT
RSVD
IIRG
RSVD
IAIG
RSVD
DR
DW
RSVD
DID
RSVD