Specification Sheet
Datasheet, Volume 2 of 2 377
PCI Express* Controller (x16) Registers
12.24 Bridge Control (BCTRL)—Offset 3Eh
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e. PCI
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge embedded within the CPU, e.g. VGA compatible address ranges
mapping.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + 3Eh
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DTSERRE
DTSTS
SDT
PDT
FB2BEN
SRESET
MAMODE
VGA16D
VGAEN
ISAEN
SERREN
PEREN
Bit
Range
Default &
Access
Field Name (ID): Description
15:12
0h
RO
Reserved (RSVD): Reserved.
11
0h
RO
DTSERRE: Discard Timer SERR# Enable: Not Applicable or Implemented. Hardwired
to 0.
10
0h
RO
DTSTS: Discard Timer Status: Not Applicable or Implemented. Hardwired to 0.
9
0h
RO
SDT: Secondary Discard Timer: Not Applicable or Implemented. Hardwired to 0.
8
0h
RO
PDT: Primary Discard Timer: Not Applicable or Implemented. Hardwired to 0.
7
0h
RO
FB2BEN: Fast Back-to-Back Enable: Not Applicable or Implemented. Hardwired to 0.
6
0h
RW
SRESET: Secondary Bus Reset: Setting this bit triggers a hot reset on the
corresponding PCI Express Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
5
0h
RO
MAMODE: Master Abort Mode: Does not apply to PCI Express. Hardwired to 0.
4
0h
RW
VGA16D: VGA 16-bit Decode: Enables the PCI-to-PCI bridge to provide 16-bit
decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB.
This bit only has meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling
VGA I/O decoding and forwarding by the bridge.
0: Execute 10-bit address decodes on VGA I/O accesses.
1: Execute 16-bit address decodes on VGA I/O accesses.
3
0h
RW
VGAEN: VGA Enable: Controls the routing of Processor initiated transactions targeting
VGA compatible I/O and memory address ranges. See the VGAEN/MDAP table in
device 0, offset 97h[0].