Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage
700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
283653-002 Datasheet 19
Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# signal is not recognized in the Normal or Auto Halt
states.
The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven
active while the processor is in the Sleep state then SLP# and STPCLK# must immediately be
driven inactive to ensure that the processor correctly initializes itself.
Input signals (other than RESET#) may not change while the processor is in the Sleep state or
transitioning into or out of the Sleep state. Input signal changes at these times will cause
unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the
Sleep state.
While in the Sleep state, the processor can enter its lowest power state, the Deep Sleep state.
Removing the processor’s input clock puts the processor in the Deep Sleep state. PICCLK may be
removed in the Sleep state.
2.2.8 Deep Sleep State
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its
context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is
in the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the
Low state.
The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the
BCLK input is restarted. Due to the PLL lock latency, there is a delay of up to 30 µsec after the
clocks have started before this state transition happens. PICCLK may be removed in the Deep
Sleep state. PICCLK should be designed to turn on when BCLK turns on when transitioning out of
the Deep Sleep state.
The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except
that RESET# assertion will result in unpredictable behavior.
Table 3. Clock State Characteristics
Clock State Exit Latency Snooping? System Uses
Normal N/A Yes Normal program execution
Auto Halt Approximately 10 bus clocks Yes S/W controlled entry idle mode
Stop Grant 10 bus clocks Yes H/W controlled entry/exit mobile throttling
Quick Start Through snoop, to HALT/Grant
Snoop state: immediate
Through STPCLK#, to Normal
state: 8 bus clocks
Yes H/W controlled entry/exit mobile throttling
HALT/Grant
Snoop
A few bus clocks after the end
of snoop activity
Yes Supports snooping in the low power states
Sleep To Stop Grant state 10 bus
clocks
No H/W controlled entry/exit desktop idle mode
support
Deep Sleep
30 µsec
No H/W controlled entry/exit mobile powered-on
suspend support
NOTE: See Table 33 for power dissipation in the low-power states.