Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
34 Datasheet 283653-002
Table 16. CMOS and Open-drain Signal Groups AC Specifications
1, 2
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 0.975V ±25 mV or 1.10V ±80 mV or 1.15V ±80
mV or 1.35V ±100 mV or 1.60V ±115 mV or 1.70V -80/+125 mV ; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T14 1.5V Input Pulse Width, except PWRGOOD and
LINT[1:0]
2 BCLKs Figure 8 Active and
Inactive states
T14B LINT[1:0] Input Pulse Width 6 BCLKs Figure 8 Note 3
T15 PWRGOOD Inactive Pulse Width 10 BCLKs Figure 11 Notes 4, 5
NOTES:
1. All AC timings for CMOS and Open-drain signals are referenced to the BCLK rising edge at 1.25V. All
CMOS and Open-drain signals are referenced at 0.75V.
2. Minimum output pulse width on CMOS outputs is 2 BCLKs.
3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as
an edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4. When driven inactive, or after V
CC
, V
CCT
and BCLK become stable. PWRGOOD must remain below V
IL25,max
from Table 12 until all the voltage planes meet the voltage tolerance specifications in Table 9A and BCLK
has met the BCLK AC specifications in Table 13 for at least 10 clock cycles. PWRGOOD must rise glitch-
free and monotonically to 2.5V.
5. If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD
Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.
PWRGOOD must still remain below V
IL25,max
until all the voltage planes meet the voltage tolerance
specifications.
Table 17. Reset Configuration AC Specifications
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 0.975V ±25 mV or 1.10V ±80 mV or 1.15V ±80
mV or 1.35V ±100 mV or 1.60V ±115 mV or 1.70V -80/+125 mV ; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T16 Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Setup Time
4 BCLKs
Figure 8.
Figure 9
Before
deassertion of
RESET#
T17 Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Hold Time
2 20 BCLKs
Figure 8.
Figure 9
After clock that
deasserts
RESET#
T18 RESET#/PWRGOOD Setup Time 1 ms Figure 11 Before
deassertion of
RESET#
1
NOTE: At least 1 ms must pass after PWRGOOD rises above V
IH25,min
from Table 12 and BCLK meets its
AC timing specification until RESET# may be deasserted.