Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage
700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
283653-002 Datasheet 35
Table 18. APIC Bus Signal AC Specifications
1
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 0.975V ±25 mV or 1.10V ±80 mV or 1.15V ±80
mV or 1.35V ±100 mV or 1.60V ±115 mV or 1.70V -80/+125 mV ; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T21 PICCLK Frequency 2 33.3 MHz Note 2
T22 PICCLK Period 30 500 ns Figure 6
T23 PICCLK High Time 10.5 ns Figure 6 at>1.7V
T24 PICCLK Low Time 10.5 ns Figure 6 at<0.7V
T25 PICCLK Rise Time 0.25 3.0 ns Figure 6 (0.7V – 1.7V)
T26 PICCLK Fall Time 0.25 3.0 ns Figure 6 (1.7V – 0.7V)
T27 PICD[1:0] Setup Time 5.0 ns Figure 9 Note 3
T28 PICD[1:0] Hold Time 2.5 ns Figure 9 Note 3
T29 PICD[1:0] Valid Delay (Rising Edge)
PICD[1:0] Valid Delay (Falling Edge)
1.5
1.5
8.7
12.0
Ns
ns
Figure 8 Notes 3, 4, 5
NOTES:
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.25V. All CMOS signals are
referenced at 0.75V.
2. The minimum frequency is 2 MHz when PICD0 is at 1.5V at reset. If PICD0 is strapped to V
SS
at reset then
the minimum frequency is 0 MHz.
3. Referenced to PICCLK Rising Edge.
4. For Open-drain signals, Valid Delay is synonymous with Float Delay.
5. Valid delay timings for these signals are specified into 150Ω to 1.5V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.