Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
36 Datasheet 283653-002
Table 19. TAP Signal AC Specifications
1
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 0.975V ±25 mV or 1.10V ±80 mV or 1.15V ±80
mV or 1.35V ±100 mV or 1.60V ±115 mV or 1.70V -80/+125 mV ; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T30 TCK Frequency — 16.67 MHz
T31 TCK Period 60 — ns Figure 6
T32 TCK High Time 25.0 ns Figure 6
≥ 1.2V, Note 2
T33 TCK Low Time 25.0 ns Figure 6
≤ 0.6V, Note 2
T34 TCK Rise Time 5.0 ns Figure 6 (0.6V – 1.2V), Notes 2, 3
T35 TCK Fall Time 5.0 ns Figure 6 (1.2V – 1.6V), Notes 2, 3
T36 TRST# Pulse Width 40.0 ns Figure 13 Asynchronous, Note 2
T37 TDI, TMS Setup Time 5.0 ns Figure 12 Note 4
T38 TDI, TMS Hold Time 14.0 ns Figure 12 Note 4
T39 TDO Valid Delay 1.0 10.0 ns Figure 12 Notes 5, 6
T40 TDO Float Delay 25.0 ns Figure 12 Notes 2, 5, 6
T41 All Non-Test Outputs Valid Delay 2.0 25.0 ns Figure 12 Notes 5, 7, 8
T42 All Non-Test Outputs Float Delay 25.0 ns Figure 12 Notes 2, 5, 7, 8
T43 All Non-Test Inputs Setup Time 5.0 ns Figure 12 Notes 4, 7, 8
T44 All Non-Test Inputs Hold Time 13.0 ns Figure 12 Notes 4, 7, 8
NOTES:
1. All AC timings for TAP signals are referenced to the TCK rising edge at 0.75V. All TAP and CMOS signals
are referenced at 0.75V.
2. Not 100% tested. Specified by design/characterization.
3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4. Referenced to TCK rising edge.
5. Referenced to TCK falling edge.
6. Valid delay timing for this signal is specified into 150Ω terminated to 1.5V and 0 pF of external load. For
real system timings these specifications must be derated for external capacitance at 105 ps/pF.
7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to boundary scan operations.
8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.
Table 20. Quick Start/Deep Sleep AC Specifications
1
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 0.975V ±25 mV or 1.10V ±80 mV or 1.15V
±80 mV or 1.35V ±100 mV or 1.60V ±115 mV or 1.70V -80/+125 mV ; V
CCT
= 1.50V ±115 mV
Symbol Parameter Min Max Unit Figure Notes
T45 Stop Grant Cycle Completion to Clock Stop 100 BCLKs Figure 14
T46 Stop Grant Cycle Completion to Input Signals Stable 0
µs
Figure 14
T47 Deep Sleep PLL Lock Latency 0 30
µs
Figure 14,
Figure 15
Note 2
T48 STPCLK# Hold Time from PLL Lock 0 ns Figure 14
T49 Input Signal Hold Time from STPCLK# Deassertion 8 BCLKs Figure 14
NOTES:
1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2. The BCLK Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.