Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
42 Datasheet 283653-002
Figure 13. Test Reset Timings
TRST#
0.75V
T
q
D0009-01
NOTE:
T
q
= T36 (TRST# Pulse Width)
Figure 14. Quick Start/Deep Sleep Timing
T
w
stpgnt
Running
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals
Changing
Normal Quick Start Deep Sleep
Quick Start
Normal
Frozen
T
v
T
y
T
z
T
x
V0010-00
NOTES:
T
v
= T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)
T
w
= T46 (Setup Time to Input Signal Hold Requirement)
T
x
= T47 (Deep Sleep PLL Lock Latency)
T
y
= T48 (PLL lock to STPCLK# Hold Time)
T
z
= T49 (Input Signal Hold Time)