Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage
700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
283653-002 Datasheet 43
Figure 15. Stop Grant/Sleep/Deep Sleep Timing
T
u
stpgnt
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals
FrozenChanging
Normal
Stop
Grant
Sleep Deep Sleep Sleep
Stop
Grant
Normal
Running
T
t
T
v
T
y
T
z
T
w
T
x
V0011-00
Changing
NOTES:
T
t
= T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
T
u
= T51 (Setup Time to Input Signal Hold Requirement)
T
v
= T52 (SLP# assertion to clock shut off delay)
T
w
= T47 (Deep Sleep PLL lock latency)
T
x
= T54 (SLP# Hold Time)
T
y
= T55 (STPCLK# Hold Time)
T
z
= T56 (Input Signal Hold Time)
Figure 16. Intel SpeedStep Technology/Deep Sleep Timing
BCLK
V
IL25
BCLK off
BCLK on
(out of spec)
BCLK on
(in spec)
1.25V1.25V
BCLK on
T
s
V0036-00
GHI#
T
h
T
y
T
x
NOTES:
T
s
= T57 (GHI# Setup Time from BCLK Restart)
T
h
= T58 (GHI# Hold Time from BCLK Restart)
T
x
= T59 (GHI# Sample Delay)
T
y
= T60 (BCLK Settling Time)