Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
6 Datasheet 283653-002
Figures
Figure 1. Signal Groups of a Mobile Pentium III Processor/440BX AGPset - Based
System ..............................................................................................................11
Figure 2. Signal Groups of a Mobile Pentium III Processor/440MX Chipset - Based
System ..............................................................................................................12
Figure 3. Clock Control States ..........................................................................................17
Figure 4. Vcc Ramp Rate Requirement ............................................................................23
Figure 5. PLL RLC Filter....................................................................................................26
Figure 6. PICCLK/TCK Clock Timing Waveform...............................................................38
Figure 7. BCLK Timing Waveform.....................................................................................38
Figure 8. Valid Delay Timings ...........................................................................................39
Figure 9. Setup and Hold Timings.....................................................................................39
Figure 10. Cold/Warm Reset and Configuration Timings..................................................40
Figure 11. Power-on Reset Timings..................................................................................40
Figure 12. Test Timings (Boundary Scan) ........................................................................41
Figure 13. Test Reset Timings ..........................................................................................42
Figure 14. Quick Start/Deep Sleep Timing........................................................................42
Figure 15. Stop Grant/Sleep/Deep Sleep Timing..............................................................43
Figure 16. Intel SpeedStep Technology/Deep Sleep Timing............................................43
Figure 17. BCLK/PICCLK Generic Clock Waveform.........................................................45
Figure 18. Low to High, GTL+ Receiver Ringback Tolerance...........................................46
Figure 19. High to Low, GTL+ Receiver Ringback Tolerance...........................................46
Figure 20. Maximum Acceptable Overshoot/Undershoot Waveform................................47
Figure 21. Surface-mount BGA2 Package - Top and Side View ......................................50
Figure 22. Surface-mount BGA2 Package - Bottom View ................................................51
Figure 23. Socketable Micro-PGA2 Package - Top and Side View ..................................53
Figure 24. Socketable Micro-PGA2 Package - Bottom View ............................................54
Figure 25. Pin/Ball Map - Top View...................................................................................55
Figure 26. PWRGOOD Relationship at Power On............................................................74
Figure 27. PLL Filter Specifications ..................................................................................83