Datasheet

Mobile Intel

Pentium

III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,

900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage

700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz

283653-002 Datasheet 71

appropriate pins/balls on both agents on the system bus if they are used. During power-on

configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking.

DRDY# (I/O - GTL+)

The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating

valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle

clocks. This signal must be connected to the appropriate pins/balls on both agents on the system

bus.

EDGCTRLP (Analog)

The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the GTL+ output

buffers. Connect the signal to V

with a 110-Ω, 1% resistor.

FERR# (O - 1.5V Tolerant Open-drain)

The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked

floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it

is included for compatibility with systems using DOS-type floating-point error reporting.

FLUSH# (I - 1.5V Tolerant)

When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache

lines in the Modified state and invalidates all internal cache lines. At the completion of a flush

operation, the processor issues a Flush Acknowledge transaction. The processor stops caching any

new data while the FLUSH# signal remains asserted.

On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to

determine its power-on configuration.

GHI# (I - 1.5V Tolerant)

The GHI# signal controls which operating mode bus ratio is selected in a mobile Pentium III

processor featuring Intel SpeedStep technology. On the processor featuring Intel SpeedStep

technology, this signal is latched when BCLK restarts in Deep Sleep state and determines which

of two bus ratios is selected for operation. This signal is ignored when the processor is not in the

Deep Sleep state. This signal is a “Don’t Care” on processors that do not feature Intel SpeedStep

technology. This signal has an on-die pull-up to V

CCT

and should be driven with an Open-drain

driver with no external pull-up.

HIT# (I/O - GTL+), HITM# (I/O - GTL+)

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation

results, and must be connected to the appropriate pins/balls on both agents on the system bus.