Datasheet

Mobile Intel

Pentium

III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,

900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage

700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz

283653-002 Datasheet 75

agents will deassert their outputs within two clocks. RESET# is the only GTL+ signal that does

not have on-die GTL+ termination. A 56.2Ω 1% terminating resistor connected to V

CCT

required.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-

on configuration. The configuration options are described in Section 4 and in the Pentium

Processor Developer’s Manual.

Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive

transition of RESET#, the processor optionally executes its built-in self-test (BIST) and begins

program execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the

appropriate pins/balls on both agents on the system bus.

RP# (I/O - GTL+)

The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on

ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on

the system bus.

A correct parity signal is high if an even number of covered signals are low and low if an odd

number of covered signals are low. This definition allows parity to be high when all covered

signals are high.

RS[2:0]# (I - GTL+)

The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for

completion of the current transaction) and must be connected to the appropriate pins/balls on both

agents on the system bus.

RSP# (I - GTL+)

The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity

protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on

the system bus.

A correct parity signal is high if an even number of covered signals are low, and it is low if an odd

number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also

high since it is not driven by any agent guaranteeing correct parity.

RSVD (TBD)

The RSVD (Reserved) signal is currently unimplemented but is reserved for future use. Leave this

signal unconnected. Intel recommends that a routing channel for this signal be allocated.