Datasheet

Mobile Intel

Pentium

III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,

900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,

Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz

76 Datasheet 283653-002

RTTIMPEDP (Analog)

The RTTIMPEDP (R

Impedance/PMOS) signal is used to configure the on-die GTL+

termination. Connect the RTTIMPEDP signal to V

with a 56.2-Ω, 1% resistor.

SLP# (I - 1.5V Tolerant)

The SLP# (Sleep) signal, when asserted in the Stop Grant state, causes the processor to enter the

Sleep state. During the Sleep state, the processor stops providing internal clock signals to all units,

leaving only the Phase-Locked Loop (PLL) still running. The processor will not recognize snoop

and interrupts in the Sleep state. The processor will only recognize changes in the SLP#,

STPCLK# and RESET# signals while in the Sleep state. If SLP# is deasserted, the processor exits

Sleep state and returns to the Stop Grant state in which it restarts its internal clock to the bus and

APIC processor units.

SMI# (I - 1.5V Tolerant)

The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On

accepting a System Management Interrupt, the processor saves the current state and enters System

Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins

program execution from the SMM handler.

STPCLK# (I - 1.5V Tolerant)

The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Stop

Grant state. The processor issues a Stop Grant Acknowledge special transaction and stops

providing internal clock signals to all units except the bus and APIC units. The processor

continues to snoop bus transactions and service interrupts while in the Stop Grant state. When

STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution.

The assertion of STPCLK# has no affect on the bus clock.

TCK (I - 1.5V Tolerant)

The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test

access port).

TDI (I - 1.5V Tolerant)

The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial

input needed for JTAG support.

TDO (O - 1.5V Tolerant Open-drain)

The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the

serial output needed for JTAG support.