Datasheet

Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,
Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
80 Datasheet 283653-002
8.2 Signal Summaries
Table 38 through Table 41 list the attributes of the processor input, output, and I/O signals.
Table 38. Input Signals
Name Active Level Clock Signal Group Qualified
A20M# Low Asynch CMOS Always
BCLK High — System Bus Always
BPRI# Low BCLK System Bus Always
BSEL[1:0] High Asynch Implementation Always
DEFER# Low BCLK System Bus Always
FLUSH# Low Asynch CMOS Always
GHI# Low Asynch CMOS Deep Sleep state
IGNNE# Low Asynch CMOS Always
INIT# Low Asynch System Bus Always
INTR High Asynch CMOS APIC disabled mode
LINT[1:0] High Asynch APIC APIC enabled mode
NMI High Asynch CMOS APIC disabled mode
PICCLK High — APIC Always
PREQ# Low Asynch Implementation Always
PWRGOOD High Asynch Implementation Always
RESET# Low BCLK System Bus Always
RS[2:0]# Low BCLK System Bus Always
RSP# Low BCLK System Bus Always
SLP# Low Asynch Implementation Stop Grant state
SMI# Low Asynch CMOS Always
STPCLK# Low Asynch Implementation Always
TCK High — JTAG
TDI TCK JTAG
TMS TCK JTAG
TRDY# Low BCLK System Bus Response phase
TRST# Low Asynch JTAG
Table 39. Output Signals
Name Active Level Clock Signal Group
FERR# Low Asynch Open-drain
IERR# Low Asynch Open-drain
PRDY# Low BCLK Implementation
TDO High TCK JTAG
VID[4:0] High Asynch Implementation