Specification Update

Summary Tables of Changes
Specification Update 15
Steppings
NO.
B-1 CPU
Signature
= 06D6h
C-0 CPU
Signature
= 06D8h
B-1 CPU
Signature
= 0695h
C-0 CPU
Signature
= 06E8h
D-0 CPU
Signature
= 06ECh
B-2 CPU
Signature
= 06F6h
A-1 CPU
Signature
= 10661h
Plans
ERRATA
W23 X X X X X X X No Fix
VM Bit Will Be Cleared on
Second Fault Handled by
Task Switch from Virtual-
8086 (VM86)
W24 X X X No Fix
Code Fetch Matching
Disabled Debug Register
May Cause Debug
Exception
W25 X X X No Fix
Upper Four PAT Entries
Not Usable with Mode B or
Mode C Paging
W26 X X X X
X
No Fix
SSE/SSE2 Streaming
Store Resulting in a Self-
Modifying Code (SMC)
Event May Cause
Unexpected Behavior
W27 X X No Fix
Error in Instruction Fetch
Unit (IFU) Can Result in
an Erroneous Machine
Check-Exception (#MC)
W28
Removed, see Erratum
W3
W29
Removed, see Erratum
W4
W30
Removed, see Erratum
W5
W31 X X X X X X No Fix
Page with PAT (Page
Attribute Table) Set to
USWC (Uncacheable
Speculative Write
Combine) While
Associated MTRR (Memory
Type Range Register) Is
UC (Uncacheable) May
Consolidate to UC
W32 X X X X X No Fix
Under Certain Conditions
LTR (Load Task Register)
Instruction May Result in
System Hang