Specification Update

Summary Tables of Changes
20 Specification Update
Steppings
NO.
B-1 CPU
Signature
= 06D6h
C-0 CPU
Signature
= 06D8h
B-1 CPU
Signature
= 0695h
C-0 CPU
Signature
= 06E8h
D-0 CPU
Signature
= 06ECh
B-2 CPU
Signature
= 06F6h
A-1 CPU
Signature
= 10661h
Plans
ERRATA
W73 X X X X X No Fix
SYSENTER/SYSEXIT
Instructions Can Implicitly
Load “Null Segment
Selector” to SS and CS
Registers
W74 X X X X X X X No Fix
Using 2-M/4-M Pages
When A20M# Is Asserted
May Result in Incorrect
Address Translations
W75 X X X X No Fix
CPUID Extended Feature
Does Not Report Intel®
Thermal Monitor 2
Support Correctly
W76
Removed Erratum Due to
Redundancy
W77
Removed Erratum Due to
Redundancy
W78 X X X X X X No Fix
Premature Execution of a
Load Operation Prior to
Exception Handler
Invocation
W79 X X X X No Fix
Performance Monitoring
Events for Retired
Instructions (C0H) May
Not Be Accurate
W80 X X X X X X No Fix
#GP Fault Is NOT
Generated on Writing
IA32_MISC_ENABLE [34]
When Execute Disable Bit
is Not Supported
W81 Removed Erratum
W82
Removed Erratum- See
W26
W83 X X X X No Fix
Writing Shared Unaligned
Data that Crosses a Cache
Line without Proper
Semaphores or Barriers
May Expose a Memory
Ordering Issue