Specification Update

Summary Tables of Changes
Specification Update 21
Steppings
NO.
B-1 CPU
Signature
= 06D6h
C-0 CPU
Signature
= 06D8h
B-1 CPU
Signature
= 0695h
C-0 CPU
Signature
= 06E8h
D-0 CPU
Signature
= 06ECh
B-2 CPU
Signature
= 06F6h
A-1 CPU
Signature
= 10661h
Plans
ERRATA
W84 X X X X No Fix
MSRs Actual Frequency
Clock Count (IA32_APERF)
or Maximum Frequency
Clock Count
(IA32_MPERF) May
Contain Incorrect Data
after a Machine Check
Exception (MCE)
W85 X X X X X X X No Fix
Incorrect Address
Computed For Last Byte of
FXSAVE/FXRSTOR Image
Leads to Partial Memory
Update
W86 X X X X X X X No Fix
Values for LBR/BTS/BTM
will be Incorrect after an
Exit from SMM
W87 X X X X No Fix
Using Memory Type
Aliasing with Memory
Types WB/WT May Lead
to Unpredictable Behavior
W88 X X X X No Fix
Performance Monitoring
Event FP_ASSIST May Not
be Accurate
W89 X X X X X X X No Fix
The BS Flag in DR6 May
Be Set for Non-Single-
Step #DB Exception
W90 X X X X X X No Fix
BTM/BTS Branch-From
Instruction Address May
Be Incorrect for Software
Interrupts
W91 Removed Erratum
W92 x x x x x x X No Fix
Unaligned Accesses to
Paging Structures May
Cause the Processor to
Hang
W93 x x x x x x X No Fix
INVLPG Operation for
Large (2M/4M) Pages May
be Incomplete under
Certain Conditions
W94 x x x x x x X No Fix
Page Access Bit May be
Set Prior to Signaling a
Code Segment Limit Fault