Specification Update

Errata
34 Specification Update
Errata
W1. Performance Monitoring Event That Counts the Number of
Instructions Decoded (D0h) Is Not Accurate
Problem: The performance-monitoring event that counts the number of
instructions decoded may have inaccurate results.
Implication: There is no functional impact of this erratum. However, the
results/counts from this performance monitoring event should not be
considered as being accurate
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W2. RDTSC Instruction May Report the Wrong Time-Stamp
Counter Value
Problem: The time-stamp counter is a 64-bit counter that is read in two, 32-bit
chunks. The counter incorrectly advances and therefore the two chunks
may go out of synchronization causing the Read Time-stamp Counter
(RDTSC) instruction to report the wrong time-stamp counter value.
Implication: This erratum may cause software to see the wrong representation of
processor time and may result in unpredictable software operation.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
W3. Code Segment Limit Violation May Occur on 4-GB Limit
Check
Problem: Code Segment limit violation may occur on 4-GB limit check when the
code stream wraps around in a way that one instruction ends at the last
byte of the segment and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not
observed this erratum with any commercially-available software, or
system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.