Specification Update

Errata
Specification Update 35
W4. FST Instruction with Numeric and Null Segment
Exceptions May Take Numeric Exception with Incorrect
FPU Operand Pointer
Problem: If execution of an FST (Store Floating Point Value) instruction would
generate both numeric and null segment exceptions, the numeric
exception may be taken first and with the Null x87 FPU Instruction
Operand (Data) Pointer.
Implication: Due to this erratum, on an FST instruction the processor reports a
numeric exception instead of reporting an exception because of a Null
segment. If the numeric exception handler tries to access the FST data
it will get a #GP fault. Intel has not observed this erratum with any
commercially available software, or system.
Workaround: The numeric exception handler should check the segment and if it is Null avoid further
access to the data that caused the fault.
Status: For affected steppings see the Summary Table of Changes.
W5. Code Segment (CS) Is Wrong on SMM Handler When
SMBASE Is Not Aligned
Problem: With SMBASE being relocated to a non-aligned address, during SMM
entry the CS can be improperly updated which can lead to an incorrect
SMM handler.
Implication: This is a rare condition that may result in a system hang. Intel has not
observed this erratum with any commercially-available software, or
system.
Workaround: Align SMBASE to 32 kB.
Status: For the steppings affected, see the Summary Tables of Changes.
W6. A Locked Data Access That Spans across Two Pages May
Cause the System to Hang
Problem: An instruction with lock data access that spans across two pages may,
given some rare internal conditions, hang the system.
Implication: When this erratum occurs, the system may hang. Intel has not
observed this erratum with any commercially-available software or
system.
Workaround: A locked data access should always be aligned.
Status: For the steppings affected, see the Summary Tables of Changes.