Specification Update

Errata
40 Specification Update
W16. Unable to Disable Reads/Writes to Performance
Monitoring Related MSRs
Problem: The Performance Monitoring Available bit in the miscellaneous
processor features MSR (IA32_MISC_ENABLES.7) was defined so that
when it is cleared to a 0, RDMSR/WRMSR/RDPMC instructions would
return all zeros for reads of and prevent any writes to performance
monitoring related MSRs. Currently it is possible to read from or write
to performance monitoring related MSRs when the Performance
Monitoring Available bit is cleared to a 0.
Implication: It is not possible to disallow reads and writes to the Performance
Monitoring MSRs. Intel has not observed this erratum with any
commercially-available software or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W17. Move to Control Register Instruction May Generate a
Breakpoint Report
Problem: A move (MOV) to control register (CR) instruction where control
register is CR0, CR3 or CR4 may generate a breakpoint report.
Implication: MOV to control register instruction is not expected to generate a
breakpoint report.
Workaround: Ignore breakpoint data from MOV to CR instruction.
Status: For the steppings affected, see the Summary Tables of Changes.