Specification Update

Errata
Specification Update 43
W21. POPF and POPFD Instructions That Set the Trap Flag Bit
May Cause Unpredictable Processor Behavior
Problem: In some rare cases, POPF and POPFD instructions that set the Trap Flag
(TF) bit in the EFLAGS register (causing the processor to enter Single-
Step mode) may cause unpredictable processor behavior.
Implication: Single step operation is typically enabled during software debug
activities, not during normal system operation.
Workaround: There is no workaround for single step operation in commercially-available software.
For debug activities on custom software the POPF and POPFD instructions could be
immediately followed by a NOP instruction to facilitate correct execution.
Status: For the steppings affected, see the Summary Tables of Changes.
W22. Performance Event Counter Returns Incorrect Value on
L2_LINES_IN Event
Problem: The performance event counter returns an incorrect value on
L2_LINES_IN event (EMON event #24H) when the L2 cache is disabled.
Implication: Due to this erratum, L2_LINES_IN performance event counter should
not be monitored while the L2 cache is disabled. This erratum has no
functional impact.
Workaround: Ignore L2_LINES_IN event when the L2 cache is disabled.
Status: For the steppings affected, see the Summary Tables of Changes.
W23. VM Bit Is Cleared on Second Fault Handled by Task Switch
from Virtual-8086 (VM86)
Problem: Following a task switch to any fault handler that was initiated while the
processor was in VM86 mode, if there is an additional fault while
servicing the original task switch then the VM bit will be incorrectly
cleared in EFLAGS, data segments will not be pushed and the processor
will not return to the correct mode upon completion of the second fault
handler via IRET.
Implication: When the OS recovers from the second fault handler, the processor will
no longer be in VM86 mode. Normally, operating systems should
prevent interrupt task switches from faulting, thus the scenario should
not occur under normal circumstances.
Workaround: None identified.
Status: For the steppings affected, see the see the Summary Tables of Changes.