Specification Update

Errata
44 Specification Update
W24. Code Fetch Matching Disabled Debug Register May Cause
Debug Exception
Problem: The bits L0-3 and G0-3 enable breakpoints local to a task and global to
all tasks, respectively. If one of these bits is set, a breakpoint is
enabled, corresponding to the addresses in the debug registers DR0-
DR3. If at least one of these breakpoints is enabled, any of these
registers are disabled (i.e., Ln and Gn are 0), and RWn for the disabled
register is 00 (indicating a breakpoint on instruction execution),
normally an instruction fetch will not cause an instruction-breakpoint
fault based on a match with the address in the disabled register(s).
However, if the address in a disabled register matches the address of a
code fetch which also results in a page fault, an instruction-breakpoint
fault will occur.
Implication: While debugging software, extraneous instruction-breakpoint faults
may be encountered if breakpoint registers are not cleared when they
are disabled. Debug software which does not implement a code
breakpoint handler will fail, if this occurs. If a handler is present, the
fault will be serviced. Mixing data and code may exacerbate this
problem by allowing disabled data breakpoint registers to break on an
instruction fetch.
Workaround: The debug handler should clear breakpoint registers before they become disabled.
Status: For the steppings affected, see the Summary Tables of Changes.
W25. Upper Four PAT Entries Not Usable with Mode B or Mode C
Paging
Problem: The page attribute table (PAT) contains eight entries, which must all be
initialized and considered when setting up memory types for the
Pentium III processor. However, in Mode B or Mode C paging, the
upper four entries do not function correctly for 4-Kbyte pages.
Specifically, bit 7 of page table entries that translate addresses to 4-
Kbyte pages should be used as the upper bit of a 3-bit index to
determine the PAT entry that specifies the memory type for the page.
When Mode B (CR4.PSE = 1) and/or Mode C (CR4.PAE) are enabled,
the processor forces this bit to zero when determining the memory type
regardless of the value in the page table entry. The upper four entries
of the PAT function correctly for 2-Mbyte and 4-Mbyte large pages
(specified by bit 12 of the page directory entry for those translations).
Implication: Only the lower four PAT entries are useful for 4-kB translations when
Mode B or C paging is used. In Mode A paging (4-Kbyte pages only), all
eight entries may be used. All eight entries may be used for large
pages in Mode B or C paging.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.