Specification Update

Errata
Specification Update 45
W26. SSE/SSE2 Streaming Store Resulting in a Self-Modifying
Code (SMC) Event May Cause Unexpected Behavior
Problem: An SSE or SSE2 streaming store that results in a self-modifying code
(SMC) event may cause unexpected behavior. The SMC event occurs on
a full address match of code contained in L1 cache.
Implication: Due to this erratum, any of the following events may occur:
1. A data access break point may be incorrectly reported on the instruction pointer
(IP) just before the store instruction.
2. A non-cacheable store can appear twice on the external bus (the first time it will
write only 8 bytes, the second time it will write the entire 16 bytes).
Intel has not observed this erratum with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W27. Error in Instruction Fetch Unit (IFU) Can Result in an
Erroneous Machine Check-Exception (#MC)
Problem: A rare combination of events including the generation of a bus lock(s),
the execution of a WBINVD instruction, and a page accessed or dirty bit
assist may result in an erroneous Machine Check-Exception (#MC).
Implication: Due to this erratum, unexpected machine check-exception (#MC) is
generated. Intel has not been able to reproduce this erratum with
commercially-available software.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
W28. Removed; See Erratum W3.
W29. Removed; See Erratum W4.
W30. Removed; See Erratum W5.