Specification Update

Errata
46 Specification Update
W31. Page with PAT (Page Attribute Table) Set to USWC
(Uncacheable Speculative Write Combine) While
Associated MTRR (Memory Type Range Register) Is UC
(Uncacheable) May Consolidate to UC
Problem: A page whose PAT memory type is USWC while the relevant MTRR
memory type is UC, the consolidated memory type may be treated as
UC (rather than WC, as specified in the Intel® 64 and IA-32
Architecture Software Developer’s Manual).
Implication: When this erratum occurs, the memory page may be as UC (rather
than WC). This may have a negative performance impact.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W32. Under Certain Conditions LTR (Load Task Register)
Instruction May Result in System Hang
Problem: A LTR instruction may result in a system hang if all the following
conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
3. Data BP (breakpoint) is set on cache line containing the descriptor data.
Implication: This erratum may result in system hang if all conditions have been met.
This erratum has not been observed in commercial operating systems
or software. For performance reasons, GDT is typically aligned to 8-
bytes.
Workaround: Align GDT to 8 bytes.
Status: For the steppings affected, see the Summary Tables of Changes.
W33. Loading from Memory Type USWC (Uncacheable
Speculative Write Combine) May Get Its Data Internally
Forwarded from a Previous Pending Store
Problem: A load from memory type USWC may get its data internally forwarded
from a pending store. As a result, the expected load may never be
issued to the external bus.
Implication: When this erratum occurs, a USWC load request may be satisfied
without being observed on the external bus. There are no known usage
models where this behavior results in any negative side-effects.
Workaround: Do not use memory type USWC for memory that has read side-effects.
Status: For the steppings affected, see the Summary Tables of Changes.