Specification Update

Errata
Specification Update 49
W40. INIT Does Not Clear Global Entries in the TLB
Problem: INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address
translation due to a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE)
or CR0 (setting bits PG or PE)
registers before writing to memory early in BIOS code to clear all the global entries
from TLB.
Status: For the steppings affected, see the Summary Tables of Changes.
W41. Use of Memory Aliasing with Inconsistent Memory Type
May Cause a System Hang or a Machine Check Exception
Problem: Software that implements memory aliasing by having more than one
linear addresses mapped to the same physical page with different cache
types may cause the system to hang or to report a Machine Check
Exception (MCE). This would occur if one of the addresses is non-
cacheable used in code segment and the other a cacheable address. If
the cacheable address finds its way in instruction cache, and non-
cacheable address is fetched in IFU, the processor may invalidate the
non-cacheable address from the fetch unit. Any micro-architectural
event that causes instruction restart will expect this instruction to still
be in fetch unit and lack of it will cause a system hang or an MCE.
Implication: This erratum has not been observed with commercially-available
software.
Workaround: Although it is possible to have a single physical page mapped by two, different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency.
Status: For the steppings affected, see the Summary Tables of Changes.