Specification Update

Errata
Specification Update 51
Workaround: Software should ensure that memory accesses do not occur above the 4-G limit
(0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
W45. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory
Store Instruction May Incorrectly Increment Performance
Monitoring Count for Saturating SIMD Instructions
Retired (Event 0CFh)
Problem: Performance monitoring for Event CFH normally increments on
saturating SIMD instruction retired. Regardless of DR7 programming, if
the linear address of a retiring memory store
MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.
Implication: The value observed for performance monitoring count for saturating
SIMD instructions retired may be too high. The size of error is
dependent on the number of occurrences of the conditions described
above, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W46. Pending x87 FPU Exceptions (#MF) following STI May Be
Serviced before Higher Priority Interrupts
Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are normally serviced immediately after the instruction following the STI.
An exception to this is if the following instruction triggers a #MF. In this situation, the
interrupt should be serviced before the #MF. Because of this erratum, if following STI,
an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel
SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF
may be serviced before higher priority interrupts.
Implication: Software may observe #MF being serviced before higher priority
interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W47. Processor INIT# Will Cause a System Hang If Triggered
during an NMI Interrupt Routine Performed during
Shutdown
Problem: During the execution of an NMI interrupt handler, if shutdown occurs
followed by the INIT# signal being triggered, the processor will attempt
initialization but fail soft reset.
Implication: Due to this erratum the system may hang.
Workaround: None identified.