Specification Update

Errata
70 Specification Update
W89. The BS Flag in DR6 May Be Set for Non-Single-Step #DB
Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap
Flag, bit 8) of the EFLAGS Register is set, and a #DB (Debug
Exception) occurs due to one of the following:
• DR7 GD (General Detect, bit 13) being bit set;
• INT1 instruction;
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W90. BTM/BTS Branch-From Instruction Address May Be
Incorrect for Software Interrupts
Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is
enabled, a software interrupt may result in the overwriting of BTM/BTS
branch-from instruction address by the LBR (Last Branch Record)
branch-from instruction address.
Implication: A BTM/BTS branch-from instruction address may get
corrupted for software interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W91. Erratum Removed
W92. Unaligned Accesses to Paging Structures May Cause the
Processor to Hang
Problem: When an unaligned access is performed on paging structure entries,
accessing a portion of two different entries simultaneously, the
processor may live lock
Implication: When this erratum occurs, the processor may live lock causing a
system hang.
Workaround: Do not perform unaligned accesses on paging structure entries.
Status: For affected steppings see the Summary Table of Changes.