Specification Update

Errata
Specification Update 71
W93. INVLPG Operation for Large (2M/4M) Pages May Be
Incomplete under Certain Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-
aside Buffer (TLB) entries for large pages (2M/4M) when both of the
following conditions exist:
• Address range of the page being invalidated spans several Memory Type Range
Registers (MTRRs) with different memory types specified
• INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an
access that results in either A or D bits being set in a Page Table Entry (PTE))
Implication: Stale translations may remain valid in TLB after a PTE update resulting
in unpredictable system behavior. Intel has not observed this erratum
with any commercially available software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the same for
the entire address range of the large page.
Status: For affected steppings see the Summary Table of Changes.
W94. Page Access Bit May Be Set Prior to Signaling a Code
Segment Limit Fault
Problem: If code segment limit is set close to the end of a code page, then due to
this erratum the memory page Access bit (A bit) may be set for the
subsequent page prior to general protection fault on code segment
limit.
Implication: When this erratum occurs, a non-accessed page which is present in
memory and follows a page that contains the code segment limit may
be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable
page) as the last page of the segment or after the page that includes the code
segment limit
Status: For affected steppings see the Summary Table of Changes.