Specification Update

Errata
90 Specification Update
W140. The Stack May be Incorrect as a Result of VIP/VIF Check
on SYSEXIT and SYSRET
Problem: The stack size may be incorrect under the following scenario:
1. The stack size was changed due to a SYSEXIT or SYSRET
2. PVI (Protected Mode Virtual Interrupts) mode was enabled (CR4.PVI == 1)
3. Both the VIF (Virtual Interrupt Flag) and VIP (Virtual Interrupt Pending) flags of
the EFLAGS register are set.
Implication: If this erratum occurs the stack size may be incorrect, consequently
this result in unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W141. Performance Monitoring Event
SIMD_UOP_TYPE_EXEC.MUL Is Counted Incorrectly for
PMULUDQ Instruction
Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select
0B3H, Umask 01H) counts the number of SIMD packed multiply micro-
ops executed. The count for PMULUDQ micro-ops might be lower than
expected. No other instruction is affected.
Implication: The count value returned by the performance monitoring event
SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree
of undercount depends on actual occurrences of PMULUDQ instructions,
while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W142. Storage of PEBS Record Delayed Following Execution of
MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise
Event Based Sampling), overflow of the counter results in storage of a
PEBS record in the PEBS buffer. The information in the PEBS record
represents the state of the next instruction to be executed following the
counter overflow. Due to this erratum, if the counter overflow occurs
after execution of either MOV SS or STI, storage of the PEBS record is
delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS
record being delayed by one instruction following execution of MOV SS
or STI. The state information in the PEBS record will also reflect the
one instruction delay.
Workaround: None identified.