Specification Update

Errata
92 Specification Update
W143. Store Ordering May be Incorrect between WC and WP
Memory Types
Problem: According to Intel® 64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A, Methods of Caching Available, WP (Write
Protected) stores should drain the WC (Write Combining) buffers in the
same way as UC (Uncacheable) memory type stores do. Due to this
erratum, WP stores may not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
W144. Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code
#PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority
order relative to both code #DB (Debug Exception) and code Segment
Limit Violation #GP (General Protection Fault). Due to this erratum,
code #PF may be handled incorrectly, if all of the following conditions
are met:
• A PDE (Page Directory Entry) is modified without invalidating the corresponding
TLB (Translation Look-aside Buffer) entry
• Code execution transitions to a different code page such that both
⎯ The target linear address corresponds to the modified PDE
⎯ The PTE (Page Table Entry) for the target linear address has an A (Accessed)
bit that is clear
• One of the following simultaneous exception conditions is present following the
code transition
⎯ Code #DB and code #PF
⎯ Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before
code Segment Limit Violation #GP or processing of code #PF in lieu of
code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.