Specification Update

R
Mobile Intel® Celeron® Processor Specification Update 15
NO.
BA2
PA2
MA2
BB0
PB0
MB0
BC0
PC0
MC0
BD0
PD0
FBDO
FPDO
FBA1
FPA1
FBB1
FPB1
Plans
ERRATA
M11 X XX X X X XXXXXXXXXXX NoFix
LBER may be corrupted after some
events
M12 X XX X X X XXXXXXXXXXX NoFix
BTMs may be corrupted during
simultaneous L1 cache line
replacement
M13 X XX X X X XXXXXXXXXXX NoFix
Near CALL to ESP creates
unexpected EIP address
M14 X XX X X X XXXXXXXXXXX No Fix
Memory type undefined for non-
memory operations
M15 X XX X X X XXXXXXXXXXX NoFix
FP Data operand pointer may not be
zero after power on or Reset
M16 X XX X X X XXXXXXXXXXX NoFix
MOVD following zeroing instruction
can cause incorrect result
M17 X XX X X X XXXXXXXXXXX NoFix
Premature execution of a load
operation prior to exception handler
invocation
M18 X XX X X X XXXXXXXXXXX NoFix
Read portion of RMW instruction
may execute twice
M19 X XX X X X XXXXXXXXXXX NoFix
MC2_STATUS MSR has model-
specific error code and machine
check architecture error code
reversed
M20 X XX X X X XXXXXXXXXXX NoFix
MOV with debug register causes
debug exception
M21 X XX X X X XXXXXXXXXXX NoFix
Upper four PAT entries not usable
with Mode B or Mode C paging
M22 X XX X X X XXXXXXXXXXX NoFix
Data breakpoint exception in a
displacement relative near call may
corrupt EIP
M23 X XX X X X XXXXXXXXXXX NoFix
RDMSR and WRMSR to invalid
MSR may not cause GP fault
M24 X XX X X X XXXXXXXXXXX NoFix
SYSENTER/SYSEXIT instructions
can implicitly load null segment
selector to SS and CS registers
M25 X XX X X X XXXXXXXXXXX NoFix
PRELOAD followed by EXTEST
does not load boundary scan data
M26 X XX X X X XXXXXXXXXXX NoFix
INT 1 instruction handler execution
could generate a debug exception
M27 X XX X X X XXXXXXXXXXX NoFix
Misaligned Locked access to APIC
space results in a hang
M28 X XX X X X XXXXXXXXXXX NoFix
Processor may assert DRDY# on a
write with no data.
M29 X XX X X X XXXXXXXXXXX NoFix
GP# Fault on WRMSR to
ROB_CR_BKUPTMPDR6