Specification Update

R
Mobile Intel® Celeron® Processor Specification Update 17
NO.
BA2
PA2
MA2
BB0
PB0
MB0
BC0
PC0
MC0
BD0
PD0
FBDO
FPDO
FBA1
FPA1
FBB1
FPB1
Plans
ERRATA
M48 X XX X X X XXXXXXXXXXX NoFix
MOVD, CVTSI2SS, or PINSRW
Following Zeroing Instruction Can
Cause Incorrect Result
M49 X XX X X X XXXXXXXXXXX NoFix
FLUSH# assertion following
STPCLK# may prevent CPU clocks
from stopping
M50 X XX Fixed
Intermittent failure to assert ADS#
during processor power-on
M51 X XX Fixed
Floating-point exception signal may
be deferred
M52 X XX X X X XXXXXXX NoFix
Floating-point exception condition
may be deferred
M53 X X X NoFix
Race conditions may exist on
thermal sensor SMBus collision
detection/arbitration circuitry
M54 X XX X X X Fixed
Cache line reads may result in
eviction of invalid data
M55 X XX X X X XXXXXXXXXXX NoFix
Snoop probe during FLUSH# could
cause L2 to be left in shared state
M56 X XX X X X Fixed
Livelock may occur due to IFU line
eviction
M57 X XX Fixed
Intermittent power-on failure due to
uninitialized processor internal
nodes
M58 X XX X X X Fixed
Selector for the LTR/LLDT register
may get corrupted
M59 X XX X X X XXXXXXXXXXX NoFix
INIT does not clear global entries in
the TLB
M60 X XX X X X XXXXXXXXXXX NoFix
VM bit cleared on a double fault
handler
M61 X XX X X X XXXXXXXXXXX NoFix
Memory aliasing with inconsistent A
and D bits may cause processor
deadlock
M62 X XX X X X XXXXXXXXXXX NoFix
Use of memory aliasing with
inconsistent memory type may
cause system hang
M63 X XX X X X XXXXXXXXXXX NoFix
Processor may report invalid TSS
fault instead of Double fault during
mode C paging
M64 X XX X X X XXXXXXXXXXX NoFix
Machine check exception may occur
when interleaving code between
different memory types
M2AP X XX X X X XXXXXXXXXXX NoFix
Write to mask LVT (programmed as
EXTINT) will not deassert
outstanding interrupt