Specification Update

R
18 Mobile Intel® Celeron® Processor Specification Update
NO.
BA2
PA2
MA2
BB0
PB0
MB0
BC0
PC0
MC0
BD0
PD0
FBDO
FPDO
FBA1
FPA1
FBB1
FPB1
Plans
ERRATA
M65 X X X X X X X XXXXXXXXXX NoFix
Wrong ESP Register Values During
a Fault in VM86 Mode
M66 X X X X X X X XXXXXXXXXX NoFix
APIC ICR Write May Cause Interrupt
Not to be Sent When ICR Delivery
Bit Pending
M67 X X X X X X X XXXXXXXXXX NoFix
Processor Incorrectly Samples NMI
Interrupt after RESET# Deassertion
When Processor APIC is Hardware-
Disabled
M68 X X X X X X X XXXXXXXXXX Fix
The Instruction Fetch Unit (IFU) May
Fetch Instructions Based Upon Stale
CR3 Data After a Write to CR3
Register
M69 XXXX NoFix
Processor Might not Exit Sleep State
Properly Upon De-assertion of
CPUSLP# Signal
M70 XXXX NoFix
During Boundary Scan, BCLK Not
Sampled High When DPSLP# is
Asserted Low
M71 X X X X X X X XXXXXXXXXX NoFix
Under some complex conditions, the
instructions in the Shadow of a JMP
FAR may be Unintentionally
Executed and Retired
M72 X X X X X X X XXXXXXXXXX NoFix
Processor Does not Flag #GP on
Non-zero Write to Certain MSRs
M73 X X X X X X X XXXXXXXXXX NoFix
Lock Data Access that Spans Two
Pages May Cause the System to
Hang
M74 X X X X X X X XXXXXXXXXX NoFix
REP MOVS Operation in Fast string
Mode Continues in that Mode When
Crossing into a Page with a Different
Memory Type
M75 X X X X X X X XXXXXXXXXX NoFix
The FXSAVE, STOS, or MOVS
Instructions May Cause a Store
Ordering Violation When Data
Crosses a Page with a UC Memory
Type
M76 X X X X X X X XXXXXXXX XX NoFix
POPF and POPFD Instructions that
Set the Trap Flag Bit May Cause
Unpredictable Processor Behavior
M77 X X X X X X X XXXXXXXXXX
NoFix
Code Segment Limit Violation May
Occur on 4 Gbyte Limit Check
M78 X X X X X X X XXXXXXXX XX NoFix
FST Instruction with Numeric and
Null Segment Exceptions May take
Numeric Exception with Incorrect
FPU Operand Pointer
M79 X X X X X X X XXXXXXXXXX
NoFix
Code Segment is Wrong on SMM
Handler when SMBASE is not
Aligned