Specification Update

R
26 Mobile Intel® Celeron® Processor Specification Update
Case 2: In the second breakpoint reporting failure case, if a MOVSS or POPSS instruction with a data
breakpoint is followed by a store to memory which:
a. Crosses a 4-Kbyte page boundary,
OR
b. Causes the page table Access or Dirty (A/D) bits to be modified,the breakpoint information for the
MOVSS or POPSS will be lost. Previous processors retain this information under these boundary
conditions.
Case 3: If they occur after a MOVSS or POPSS instruction, the INTn, INTO, and INT3 instructions zero
the DR6.bi bits (bits B0 through B3), clearing pending breakpoint information, unlike previous
processors.
Case 4: If a data breakpoint and an SMI (System Management Interrupt) occur simultaneously, the SMI
will be serviced via a call to the SMM handler, and the pending breakpoint will be lost.
Case 5: When an instruction that accesses a debug register is executed, and a breakpoint is encountered
on the instruction, the breakpoint is reported twice.
Case 6: Unlike previous versions of Intel Architecture processors, Intel® Mobile Celeron® processors
will not set the Bi bits for a matching disabled breakpoint unless at least one other breakpoint is enabled.
Implication: When debugging or when developing debuggers for a Intel® Mobile Celeron® processor-based system,
this behavior should be noted. Normal usage of the MOVSS or POPSS instructions (i.e., following them
with a MOV ESP) will not exhibit the behavior of cases 1-3. Debugging in conjunction with SMM will
be limited by case 4.
Workaround: Following MOVSS and POPSS instructions with a MOV ESP instruction when using breakpoints will
avoid the first three cases of this erratum. No workaround has been identified for cases 4, 5, or 6.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M3.
Code Fetch Matching Disabled Debug Register May Cause Debug Exception
Problem: The bits L0-3 and G0-3 enable breakpoints local to a task and global to all tasks, respectively. If one of
these bits is set, a breakpoint is enabled, corresponding to the addresses in the debug registers DR0-DR3.
If at least one of these breakpoints is enabled, any of these registers are disabled (i.e., Ln and Gn are 0),
and RWn for the disabled register is 00 (indicating a breakpoint on instruction execution), normally an
instruction fetch will not cause an instruction-breakpoint fault based on a match with the address in the
disabled register(s). However, if the address in a disabled register matches the address of a code fetch
which also results in a page fault, an instruction-breakpoint fault will occur.
Implication: The bits L0-3 and G0-3 enable breakpoints local to a task and global to all tasks, respectively. If one of
these bits is set, a breakpoint is enabled, corresponding to the addresses in the debug registers DR0-DR3.
If at least one of these breakpoints is enabled, any of these registers are disabled (i.e., Ln and Gn are 0),
and RWn for the disabled register is 00 (indicating a breakpoint on instruction execution), normally an
instruction fetch will not cause an instruction-breakpoint fault based on a match with the address in the
disabled register(s). However, if the address in a disabled register matches the address of a code fetch
which also results in a page fault, an instruction-breakpoint fault will occur.
Workaround: The debug handler should clear breakpoint registers before they become disabled.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.