Specification Update

28 Mobile Intel® Celeron® Processor Specification Update

Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it happens frequently, and

produces a rounded result acceptable to most applications. The PE bit of the FPU status word may not

always be set upon receiving an inexact-result exception. Thus, if these exceptions are unmasked, a

floating-point error exception handler may not recognize that a precision exception occurred. Note that

this is a “sticky” bit, i.e., once set by an inexact-result condition, it remains set until cleared by software.

Workaround: This condition can be avoided by inserting two NOP instructions between the two floating-point

instructions.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M6.

BTM for SMI Will Contain Incorrect FROM EIP

Problem: A system management interrupt (SMI) will produce a Branch Trace Message (BTM), if BTMs are

enabled. However, the FROM EIP field of the BTM (used to determine the address of the instruction

which was being executed when the SMI was serviced) will not have been updated for the SMI, so the

field will report the same FROM EIP as the previous BTM.

Implication: A BTM which is issued for an SMI will not contain the correct FROM EIP, limiting the usefulness of

BTMs for debugging software in conjunction with System Management Mode (SMM).

Workaround: None identified

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M7.

I/O Restart in SMM May Fail After Simultaneous MCE

Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data

for this instruction becomes corrupted, the mobile processor will signal a machine check exception

(MCE). If the instruction is directed at a device which is powered down, the processor may also receive

an assertion of SMI#. Since MCEs have higher priority, the processor will call the MCE handler, and the

SMI# assertion will remain pending. However, upon attempting to execute the first instruction of the

MCE handler, the SMI# will be recognized and the processor will attempt to execute the SMM handler.

If the SMM handler is completed successfully, it will attempt to restart the I/O instruction, but will not

have the correct machine state, due to the call to the MCE handler.

Implication: A simultaneous MCE and SMI# assertion may occur for one of the I/O instructions above. The SMM

handler may attempt to restart such an I/O instruction, but will have corrupted state due to the MCE

handler call, leading to failure of the restart and shutdown of the processor.

Workaround: If a system implementation must support both SMM and MCEs, the first thing the SMM handler code

(when an I/O restart is to be performed) should do is check for a pending MCE. If there is an MCE

pending, the SMM handler should immediately exit via an RSM instruction and allow the machine check

exception handler to execute. If there is not, the SMM handler may proceed with its normal operation.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M8.

Branch Traps Do Not Function If BTMs Are Also Enabled

Problem: If branch traps or branch trace messages (BTMs) are enabled alone, both function as expected. However,

if both are enabled, only the BTMs will function, and the branch traps will be ignored.

Implication: The branch traps and branch trace message debugging features cannot be used together.

Workaround: If branch trap functionality is desired, BTMs must be disabled.